Method and system to balance ground bounce

A method, comprising:

• forming a memory cell, comprising:
• forming a write port comprising:
• connecting a first cross-coupled inverter to a second cross-coupled inverter between a first power source signal line and a second power source signal line to form a storage unit;
• connecting a first terminal of a first pass transistor to a write bit line (WBL) signal line;
• connecting a second terminal of the first pass transistor to the first cross-coupled inverter;
• connecting a first gate of the first pass transistor to a write word line (WWL) signal line;
• connecting third terminal of a second pass transistor to a write bit line bar (WBLB) signal line;
• connecting a fourth terminal of the second pass transistor to the second cross-coupled inverter;
• connecting a second gate of the second pass transistor to the WWL signal line;
• connecting a first local interconnect line in an interconnect layer to the first power source signal line;
• and
• forming a read port comprising:
• connecting a transistor to the storage unit in the write port and to the first power source signal line;
• connecting a fifth terminal of a third pass transistor to a read bit line (RBL) signal line;
• connecting a sixth terminal of the third pass transistor to the transistor;
• connecting a third gate of the third pass transistor to a read word line (RWL) signal line;
• and
• connecting a second local interconnect line in the interconnect layer to the first power source signal line, wherein:
• the second local interconnect line in the read port is separate from the first local interconnect line in the write port;
• the WWL signal line, the WBL signal line, the WBLB signal line, the RWL signal line, the RBL signal line, the first power source signal line, and the second power source signal line are formed in a conductive layer;
• and
• a layout of the conductive layer from a first edge of the memory cell to an opposite second edge of the memory cell comprises:
• the WWL signal line—the first power source signal line—the WBL signal line—the second power source signal line—the WBLB signal line—the first power source signal line—the WWL signal line—the first power source signal line—the RBL signal line—the RWL signal line.

A method, comprising:

• forming a memory array comprising a plurality of memory cells, comprising, for each memory cell of the plurality of memory cells:
• forming a cell write port comprising:
• connecting a first cross-coupled inverter to a second cross-coupled inverter between a first power source signal line and a second power source signal line to form a storage unit;
• connecting a first terminal of a first pass transistor to a write bit line (WBL) signal line;
• connecting a second terminal of the first pass transistor to the first cross-coupled inverter;
• connecting a first gate of the first pass transistor to a write word line (WWL) signal line;
• connecting third terminal of a second pass transistor to a write bit line bar (WBLB) signal line;
• connecting a fourth terminal of the second pass transistor to the second cross-coupled inverter;
• connecting a second gate of the second pass transistor to the WWL signal line;
• connecting a first local interconnect line in an interconnect layer to the first power source signal line;
• and
• forming a read port comprising:
• connecting a transistor to the storage unit and to the first power source signal line;
• connecting a fifth terminal of a third pass transistor to a read bit line (RBL) signal line;
• connecting a sixth terminal of the third pass transistor to the transistor;
• connecting a third gate of the third pass transistor to a read word line (RWL) signal line;
• and
• connecting a second local interconnect line in the interconnect layer to the first power source signal line, wherein:
• the second local interconnect line is separate from the first local interconnect line;
• the WWL signal line, the WBL signal line, the WBLB signal line, the RWL signal line, the RBL signal line, the first power source signal line, and the second power source signal line are formed in a conductive layer;
• and
• a layout of the conductive layer from a first edge of the memory cell to an opposite second edge of the memory cell comprises any one of:
• (i) the WWL signal line—the first power source signal line—the WBL signal line—the second power source signal line—the WBLB signal line—the first power source signal line—the WWL signal line—the RBL signal line—the first power source signal line—the RWL signal line, or (ii) the WWL signal line—the first power source signal line—the WBL signal line—the second power source signal line—the WBLB signal line—the first power source signal line—the WWL signal line—the first power source signal line—the RBL signal line—the RWL signal line.