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US 12,763,136 B2Granted
Dual-port static random access memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
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Abstract
A memory device includes a first SRAM cell, a second SRAM cell, a write word line (WWL) landing line, and a Vdd line. The first SRAM cell and the second SRAM cell respectively include 8 transistors. The first WWL landing line is disposed inside a cell boundary of the first SRAM cell. The Vdd line is disposed in a cell boundary of the second SRAM cell. The first WWL landing line and the Vdd line are in a same layer.
Claims20
A memory device comprising:
- a first static random access memory (SRAM) cell comprising 8 transistors;
- a second SRAM cell comprising 8 transistors;
- a first write word line (WWL) landing line disposed inside a cell boundary of the first SRAM cell;
- a Vdd line disposed inside a cell boundary of the second SRAM cell;
- and
- a read word line (RWL) landing line electrically connected to the first SRAM cell and the second SRAM cell, wherein the RWL landing line comprises a first portion disposed inside the cell boundary of the first SRAM cell and a second portion disposed inside the cell boundary of the second SRAM cell,
- wherein the RWL landing line, the first WWL landing line, and the Vdd line are in a first layer.
4 more elements
A memory device comprising:
- a first static random access memory (SRAM) cell comprising a first active region having a longest dimension extending in a first direction and a gate having a longest dimension extending in a second direction different than the first direction;
- a second SRAM cell;
- a first write word line (WWL) landing line having a longest dimension extending in the first direction and disposed inside a cell boundary of the first SRAM cell;
- a second WWL landing line having a longest dimension extending in the first direction and disposed inside a cell boundary of the second SRAM cell;
- a first Vdd line having a longest dimension extending in the first direction and disposed outside the cell boundary of the first SRAM cell and the cell boundary of the second SRAM cell;
- a second Vdd line having a longest dimension extending in the first direction and disposed outside the cell boundary of the first SRAM cell and the cell boundary of the second SRAM cell, wherein the first WWL landing line and the second WWL landing line are disposed between the first VDD line and the second VDD line along the second direction;
- and
- a read word line (RWL) landing line electrically connected to the first SRAM cell and the second SRAM cell, wherein the RWL landing line comprises a first portion disposed inside the cell boundary of the first SRAM cell and a second portion disposed inside the cell boundary of the second SRAM cell,
- wherein the first SRAM cell and the second SRAM cell are point symmetrical about a central point, and the first WWL landing line, the second WWL landing line, the first Vdd line, and the second Vdd line are in a first layer.
6 more elements
A memory device comprising:
- a first static random access memory (SRAM) cell and a second SRAM cell arranged in a first column, wherein the first SRAM cell comprises a first gate having a longest dimension extending in a first direction and the second SRAM cell comprises a second gate having a longest dimension extending in the first direction;
- a third SRAM cell and a fourth SRAM cell arranged in a second column adjacent to the first column;
- a first write word line (WWL) landing line disposed inside a cell boundary of the first SRAM cell;
- a second WWL landing line disposed inside a cell boundary of the second SRAM cell;
- a first Vdd line disposed outside the cell boundary of the first SRAM cell and the cell boundary of the second SRAM cell;
- a second Vdd line disposed outside the cell boundary of the first SRAM cell and the cell boundary of the second SRAM cell;
- and
- a read word line (RWL) landing line electrically connected to the first SRAM cell and the second SRAM cell and having a longest dimension extending in a second direction different than the first direction, wherein the RWL landing line comprises a first portion disposed inside the cell boundary of the first SRAM cell and overlying the first gate and a second portion disposed inside the cell boundary of the second SRAM cell and overlying the second gate,
- wherein the first SRAM cell, the second SRAM cell, the third SRAM cell, and the fourth SRAM cell are arranged to form a row, the second SRAM cell is adjacent to the fourth SRAM cell, and the second Vdd line is disposed in a cell boundary of the fourth SRAM cell.
6 more elements
Dependencies are inferred from the claim text.