Memory device for biasing dummy global bitline

A memory device comprising:

• first global bitlines adjacent to a first edge portion of a memory cell region;
• second global bitlines adjacent to a second edge portion of the memory cell region;
• dummy global bitlines in a central portion of the memory cell region;
• and
• a bitline sense amplifier in a sense amplifier region and connected to the first global bitlines, the second global bitlines, and the dummy global bitlines,
• wherein a first layer of the memory cell region is connected to a second layer of the sense amplifier region, said connection being through a line different from a global bitline of the memory cell region,
• wherein the second layer of the sense amplifier region is connected to at least one dummy global bitline, and
• wherein by said connection of the first layer of the memory cell region to the second layer of the sense amplifier region, the first layer is configured to apply a bias voltage to the at least one dummy global bitline.