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US 12,763,133 B2Granted
Memory die and logic die with wafer-on-wafer bond
AssigneeMicron Technology, Inc.
InventorsKunal R. Parekh, Sean S. Eilert, Aliasger T. Zaidy, Glen E. Hush
Life of this patent
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Abstract
Methods, systems, and devices related to a memory die and a logic die having a wafer-on-wafer bond therebetween. A memory die can include a memory array and a plurality of input/output (IO) lines coupled thereto. A logic die can include a deep learning accelerator (DLA). The memory die can be coupled to the logic die by a wafer-on-wafer bond. The wafer-on-wafer bond can couple the plurality of IO lines to the DLA.
Claims17
An apparatus, comprising:
- a first substrate;
- a memory die formed on a second substrate comprising a first wafer, the memory die coupled to the first substrate on a first surface of the memory die, wherein the memory die includes a plurality of dynamic random access memory (DRAM) devices;
- and
- a logic die formed on a third substrate comprising a second wafer, the logic die coupled to the memory die on a second surface of the memory die opposite the first surface by a wafer-on-wafer bond between the first wafer and the second wafer, wherein the logic die includes a plurality of logic devices, wherein at least one of the plurality of logic devices comprises a deep learning accelerator (DLA),
- wherein the wafer-on-wafer bond couples at least one of the plurality of DRAM devices directly to the DLA;
- wherein the first substrate is a different substrate than the second substrate;
- wherein the second substrate is a different substrate than the third substrate;
- wherein the third substrate is a different substrate than the first substrate;
- and
- wherein a test mode or a refresh cycle of the at least one of the plurality of DRAM devices is configured to communicate data values via local input/output lines of the at least one of the plurality of DRAM devices to and from the DLA via the wafer-on-wafer bond.
7 more elements
An apparatus, comprising:
- a substrate;
- a stack of memory dies bonded to the substrate, wherein the stack of memory dies comprises a first memory die proximal to the substrate and bonded to the substrate and a last memory die distal to the substrate;
- and
- a logic die bonded to the substrate with a plurality of bump contacts in-plane with the stack of memory dies, wherein the logic die is proximal to the last memory die and distal to the first memory die, and wherein the logic die is coupled to and in direct physical contact with the last memory die on a surface of the logic die.
1 more element
Dependencies are inferred from the claim text.