# US 12,763,129 B2 · Apparatuses and methods for input receiver circuits and receiver masks for same

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- Number: US 12,763,129 B2
- Document ID: US12763129B2
- Status: Granted
- Kind: B2
- Application number: 19/004,595
- Filed: 2024-12-30
- Published: 2025-05-01
- Granted: 2026-10-13
- Earliest claimed: 2018-10-04
- Applicants: Lodestar Licensing Group LLC
- Inventors: Dean D. Gans; John D. Porter
- Web page: https://patentgrep.com/patent/US12763129B2

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.

## Claims

### Claim 1

A method, comprising:
providing a clock to a memory device; and
providing an input signal to the memory device, wherein the input signal is outside a receiver mask defined as a hexagonal mask shape based, at least in part, on one or more voltage and timing parameters, wherein a center of the receiver mask is at a system clock cross point or the center is offset a time from a rising edge of a data clock.

### Claim 2 (depends on 1)

The method of claim 1, wherein the clock comprises a system clock and wherein the input signal comprises a command signal, an address signal, a select signal, or combinations thereof.

### Claim 3 (depends on 1)

The method of claim 1, wherein the input signal comprises a pulse.

### Claim 4 (depends on 3)

The method of claim 3, wherein the pulse is center aligned to a strobe at an internal latch circuit.

### Claim 5 (depends on 1)

The method of claim 1, wherein a pulse of the input signal is defined by a pulse width or a pulse amplitude, or both, wherein the pulse amplitude is centered around a reference voltage.

### Claim 6

An apparatus, comprising:
a memory controller configured to provide a clock to a memory device on the clock bus and to provide an input signal to the memory device, wherein the input signal does not encroach a receiver mask for the input receiver, the receiver mask defined as a hexagonal mask shape based, at least in part, on one or more voltage and timing parameters, wherein the receiver mask is offset or center aligned from a rising edge of the clock.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the clock comprises a first external clock and a second external clock, the second external clock complementary to the first external clock.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein a center of the receiver mask is aligned with a cross point of the first and second external clocks.

### Claim 9 (depends on 7)

The apparatus of claim 7, wherein the input signal comprises a command signal, address signal, select signal, or combinations thereof.

### Claim 10 (depends on 7)

The apparatus of claim 7, wherein the clock comprises a data clock, and wherein the receiver mask is center aligned at a time following a rising clock edge of the data clock.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the input signal comprises a data signal, a signal related to a data signal, or combinations thereof.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the data signal comprises a pulse, and the controller is configured to center align the pulse to a strobe at an internal latch circuit.

### Claim 13

An apparatus, comprising:
a memory including an input receiver;
a command/address bus;
a data bus;
a clock bus; and
a memory controller coupled to the memory through the command/address bus, the data bus, and the clock bus, the memory controller configured to provide a clock to a memory device on the clock bus and to provide an input signal to the memory device, wherein the input signal does not encroach a receiver mask for the input receiver, the receiver mask defined as a hexagonal mask shape based, at least in part, on one or more voltage and timing parameters, wherein a center of the receiver mask is at a system clock cross point or the center is offset a time from a rising edge of a data clock.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the input signal comprises a command signal, address signal, or a select signal provided on the command/address bus to the memory.

### Claim 15 (depends on 13)

The apparatus of claim 13, wherein the input signal comprises a data signal or a signal related to a data signal provided on the data bus to the memory.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the data signal is center aligned to a strobe at an internal latch circuit.

### Claim 17 (depends on 13)

The apparatus of claim 13, wherein the voltage parameter represents a mask height of the receiver mask.

### Claim 18 (depends on 13)

The apparatus of claim 13, wherein the receiver mask includes a first mask width at a reference voltage and further includes a second mask width at a receiver mask height.