US 12,763,124 B2 · Memory array with compensated word line access delay

Abstract

Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.

Claims19

Dependent claims

A memory device, comprising:

a first sense amplifier comprising:
a first reference capacitor coupled to a first digit line;
a second reference capacitor coupled to the first digit line;
and
switching circuitry coupled to the first reference capacitor and the second reference capacitor, the switching circuitry configured to:
receive a reference voltage;
provide the reference voltage to the first reference capacitor when a first memory cell is being activated;
and
provide the reference voltage to the second reference capacitor when a second memory cell is being activated.

6 more elements

An electronic device comprising:

a plurality of memory cells disposed between a plurality of word lines and a plurality of digit lines, wherein the plurality of memory cells comprises a target memory cell coupled to a first digit line of the plurality of digit lines;
a first sense amplifier comprising:
a first reference capacitor coupled to the first digit line;
a second reference capacitor coupled to the first digit line;
and
switching circuitry configured to provide a reference voltage to the first reference capacitor or the second reference capacitor based on a selection signal,
wherein a capacitance value of the first reference capacitor is based on a first distance between a first word line driver and the first digit line along a first word line of the plurality of word lines, and a capacitance value of the second reference capacitor is based on a second distance between a second word line driver and the first digit line along a second word line of the plurality of word lines.

4 more elements

Tangible, non-transitory, computer-readable media storing instructions that, when executed by processing circuitry, cause the processing circuitry to:

receive a first indication to read a stored value of a first target memory cell of a plurality of memory cells of a memory array;
determine that a first word line driver of the memory array is associated with the first target memory cell;
output a first selection signal based on receiving the first indication and the first target memory cell being associated with the first word line driver to a sense amplifier configured to couple to the first target memory cell, wherein the sense amplifier comprises a first reference capacitor and a second reference capacitor, and wherein the sense amplifier is configured to couple the first reference capacitor to the first target memory cell in response to receiving the first selection signal;
and
receive the stored value on the first target memory cell based on outputting the first selection signal.

2 more elements

Dependencies are inferred from the claim text.

Memory array with compensated word line access delay

Life of this patent

Memory array with compensated word line access delay

Life of this patent

Abstract

Claims19