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US 12,763,123 B2Granted
Computing circuit, memory cell, and compute-in-memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Yu Hu, Ming-Yuan Song, Xinyu Bao
Life of this patent
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Abstract
This disclosure provides a computing circuit. The computing circuit includes a first magnetic tunnel junction and a second magnetic tunnel junction. The first magnetic tunnel junction is configured to store a first logic value based on a write current. The second magnetic tunnel junction is configured to store a second logic value based on the write current. The first logic value is different from the second logic value.
Claims20
A computing circuit, comprising:
- a first magnetic tunnel junction, configured to store a first logic value based on a write current;
- and
- a second magnetic tunnel junction, configured to store a second logic value based on the write current,
- wherein the first logic value is different from the second logic value,
- the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in parallel,
- the computing circuit is configured to perform a XOR calculation or a XNOR calculation of a first input signal and a second input signal,
- the first input signal is configured to represent a direction of the write current, and
- the second input signal is configured to represent a gate voltage of a read transistor.
5 more elements
A memory cell, comprising:
- a storage circuit, configured to store data;
- and
- a computing circuit, configured to perform a calculation based on the data and comprising:
- a first magnetic tunnel junction, configured to store a first logic value based on a write current;
- and
- a second magnetic tunnel junction, configured to store a second logic value based on the write current,
- wherein the first logic value is different from the second logic value,
- the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in parallel,
- the computing circuit is configured to perform a XOR calculation or a XNOR calculation of a first input signal and a second input signal,
- the first input signal is configured to represent a direction of the write current, and
- the second input signal is configured to represent a gate voltage of a read transistor.
8 more elements
A compute-in-memory device, comprising:
- a memory array, comprising:
- a plurality of memory cells, wherein each of the memory cell comprises:
- a storage circuit, configured to store data;
- and
- computing circuit, configured to perform a calculation based on the data and comprising:
- a first magnetic tunnel junction, configured to store a first logic value based on a write current;
- and
- a second magnetic tunnel junction, configured to store a second logic value based on the write current,
- wherein the first logic value is different from the second logic value and the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in parallel;
- a plurality of word lines, respectively coupled to a row of the plurality of memory cells;
- and
- a plurality of bit lines, respectively coupled to a column of the plurality of memory cells;
- a bit line decoder, configured to select voltage signals from the plurality of bit lines according to a first address signal;
- and
- a word line decoder, configured to select the plurality of word lines according to a second address signal,
- the computing circuit is configured to perform a XOR calculation or a XNOR calculation of a first input signal and a second input signal,
- the first input signal is configured to represent a direction of the write current, and
- the second input signal is configured to represent a gate voltage of a read transistor.
15 more elements
Dependencies are inferred from the claim text.