# US 12,763,122 B2 · Read/write circuits for multi-story cross-point memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,763,122 B2 - Document ID: US12763122B2 - Status: Granted - Kind: B2 - Application number: 18/679,474 - Filed: 2024-05-31 - Published: 2025-12-04 - Granted: 2026-10-13 - Earliest claimed: 2024-05-31 - Assignees: SanDisk Technologies LLC - Applicants: Sandisk Technologies, Inc. - Inventors: Ashraf B. Islam; Jaydip Patel; Nicolas Irizarry; William Sheung - Web page: https://patentgrep.com/patent/US12763122B2 ## CPC - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/1655: {Bit-line or column circuits} - G11C 11/1657: {Word-line or row circuits} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An apparatus includes one or more control circuits to connect to a multi-story memory structure. The multi-story memory structure includes nonvolatile memory cells each having a programmable resistive element. The control circuits are configured to receive addresses of selected cells and for each selected cell determine a story in which the selected cell is located from stories including a first story between a first word line layer and a bit line layer and a second story between the bit line layer and a second word line layer. The control circuits are further configured to connect a sense amplifier to a first selected nonvolatile memory cell in the first story through a bit line of the bit line layer and connect the sense amplifier to a second selected nonvolatile memory cell in the second story through a second word line of the second word line layer. ## Claims ### Claim 1 An apparatus, comprising: one or more control circuits configured to connect to a multi-story nonvolatile memory structure that includes nonvolatile memory cells each having a programmable resistive element, the one or more control circuits configured to: receive addresses of selected nonvolatile memory cells and for each selected nonvolatile memory cell determine a story in which the selected nonvolatile memory cell is located from a plurality of stories including a first story between a first word line layer and a bit line layer and a second story between the bit line layer and a second word line layer, connect a sense amplifier to a first selected nonvolatile memory cell in the first story through a bit line of the bit line layer and a first plurality of switches while connecting a first voltage to the first selected nonvolatile memory cell through a first word line of the first word line layer and a second plurality of switches and connect the sense amplifier to a second selected nonvolatile memory cell in the second story through a second word line of the second word line layer and a third plurality of switches while connecting the first voltage to the second selected nonvolatile memory cell through the bit line and a fourth plurality of switches. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first selected nonvolatile memory cell includes a selector in contact with a first word line of the first word line layer and an MRAM cell formed between the selector and the bit line. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the second selected nonvolatile memory cell includes a selector in contact with the bit line and an MRAM cell formed between the selector and the second word line. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the one or more control circuits are further configured to connect a second voltage that is less than the first voltage to the bit line for reading the first selected nonvolatile memory cell. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the one or more control circuits are further configured to connect the second voltage to the second selected nonvolatile memory cell through the second word line. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the first voltage is a positive voltage and the second voltage is a negative voltage. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the first voltage is between 2.5 volts and 3.0 volts and the second voltage is between −2.5 volts and −3.0 volts. ### Claim 8 (depends on 5) The apparatus of claim 5, wherein the first plurality of switches and the third plurality of switches are formed by PMOS transistors and the second plurality of switches and the fourth plurality of switches are formed by NMOS transistors. ### Claim 9 A method, comprising: receiving a first address of a first selected nonvolatile memory cell at an intersection of a first word line and a first bit line in a nonvolatile memory cell structure; determining that the first selected nonvolatile memory cell is in a first story; in response to determining that the first selected nonvolatile memory cell is in the first story, connecting a sense amplifier to the first bit line to read the first selected nonvolatile memory cell; reading the first selected nonvolatile memory cell by passing a first current through the first word line, the first selected nonvolatile memory cell, the first bit line and a current mirror while the sense amplifier senses the first selected nonvolatile memory cell by comparing a sense voltage between the first bit line and the current mirror with a reference voltage; receiving a second address of a second selected nonvolatile memory cell at an intersection of the first bit line and a second word line in the nonvolatile memory cell structure; determining that the second selected nonvolatile memory cell is in a second story; in response to determining that the second selected nonvolatile memory cell is in the second story, connecting the sense amplifier to the second word line to read the second selected nonvolatile memory cell. ### Claim 10 (depends on 9) The method of claim 9, further comprising: connecting a first voltage to the first word line and a second voltage that is less than the first voltage to the first bit line to read the first selected nonvolatile memory cell. ### Claim 11 (depends on 10) The method of claim 10, further comprising: connecting the first voltage to the first bit line and the second voltage to the second word line to read the second selected nonvolatile memory cell. ### Claim 12 (depends on 11) The method of claim 11, wherein the first voltage is a positive voltage and the second voltage is a negative voltage. ### Claim 13 (depends on 12) The method of claim 12, wherein the first voltage is between 2.5 volts and 3.0 volts and the second voltage is between −2.5 volts and −3.0 volts. ### Claim 14 (depends on 9) The method of claim 9, further comprising: passing the first current through the first bit line, the second selected nonvolatile memory cell, the second word line and the current mirror to read the second selected nonvolatile memory cell; and sensing the second selected nonvolatile memory cell by the sense amplifier, including comparing a sense voltage between the second word line and the current mirror with the reference voltage while passing the first current. ### Claim 15 (depends on 9) The method of claim 9, wherein connecting the sense amplifier to the first bit line to read the first selected nonvolatile memory cell includes turning on a first plurality of NMOS transistors connected between the first bit line and the sense amplifier while a first plurality of PMOS transistors connected between the first bit line and a supply voltage are turned off and a second plurality of PMOS transistors connecting the first word line with the supply voltage are turned on. ### Claim 16 (depends on 15) The method of claim 15 wherein, connecting the sense amplifier to the second word line to read the second selected nonvolatile memory cell includes turning on a second plurality of NMOS transistors connected between the second word line and the sense amplifier while the first plurality of NMOS transistors are turned off. ### Claim 17 A system, comprising: a nonvolatile memory cell structure that includes nonvolatile memory cells in a cross-point arrangement, each memory cell having a programmable resistive element; and means for reading nonvolatile memory cells that are located in a plurality of stories including a first story between a first word line layer and a bit line layer and a second story between the bit line layer and a second word line layer including connecting a sense amplifier to a first selected nonvolatile memory cell in the first story through a bit line of the bit line layer to read the first selected nonvolatile memory cell by passing a first current through a first word line of the first word line layer, the first selected nonvolatile memory cell, the bit line and a current mirror while the sense amplifier senses the first selected nonvolatile memory cell by comparing a sense voltage between the first bit line and the current mirror with a reference voltage and connecting the sense amplifier to a second selected nonvolatile memory cell in the second story through a second word line of the second word line layer. ### Claim 18 (depends on 17) The system of claim 17, wherein each nonvolatile memory cell in the first story includes a selector located between an MRAM cell and the first word line layer, the MRAM cell located between the selector and the bit line layer and each nonvolatile memory cell in the second story includes a selector located between an MRAM cell and the bit line layer, the MRAM cell located between the selector and the second word line layer.