Semiconductor device including memory cells sharing bit lines in write operation

A semiconductor device which includes a plurality of memory cells, the semiconductor device comprising:

• a first memory cell;
• a second memory cell disposed adjacent to the first memory cell along a first direction;
• a first bit line extending in a second direction perpendicular to the first direction and connected to the first memory cell;
• a second bit line and a third bit line extending in the second direction between the first memory cell and the second memory cell and connected to the first memory cell and the second memory cell;
• a first word line extending in the first direction and connected to the first memory cell;
• a second word line extending in the first direction and connected to the second memory cell;
• and
• a control unit connected to the first bit line, the second bit line, the third bit line, the first word line and the second word line,
• wherein the control unit is configured to:
• perform a read operation on the first memory cell by using the first word line and the first bit line;
• perform a write operation on the first memory cell by using the first word line, the second bit line and the third bit line;
• and
• perform a write operation on the second memory cell by using the second word line, the second bit line and the third bit line.