Nonvolatile memory interface circuit, storage device having the same and method of operating the same

A nonvolatile memory interface circuit comprising:

• a first delay line configured to receive a data signal and output a delayed data signal;
• a second delay line configured to receive a data strobe signal and output a plurality of sampling data strobe signals by delaying the data strobe signal;
• an output circuit configured to output the delayed data signal as read data in response to the data strobe signal;
• and
• an off-chip compensation logic configured to detect off-chip variation in real time by comparing the read data with sampling data corresponding to the plurality of sampling data strobe signals, and to compensate for the off-chip variation.

A storage device comprising:

• at least one nonvolatile memory device;
• and
• a controller configured to control the at least one nonvolatile memory device,
• wherein the controller includes a nonvolatile memory interface circuit configured to communicate with the at least one nonvolatile memory device through at least one channel,
• wherein the nonvolatile memory interface circuit includes:
• a margin collector configured to collect margin information by comparing read data with sampling data;
• an on-chip margin search logic configured to track a valid window margin by adjusting an offset value based on the margin information;
• and
• a compensation calculator configured to determine off-chip variation corresponding to the offset value when the valid window margin is in a margin lock state.