Impedance calibration circuits and semiconductor memory devices including the same

A semiconductor memory device comprising:

• an external resistor provided in a board;
• and
• a plurality of memory dies mounted on the board and commonly connected to the external resistor,
• wherein each of the plurality of memory dies includes an impedance calibration circuit connected to the external resistor through an impedance pad,
• wherein the impedance calibration circuit, in response to an impedance calibration command, is configured to perform an impedance calibration operation by:
• generating a first reference voltage code based on a voltage level of a selected reference voltage becoming the same as a first voltage of a first node coupled to the impedance pad, the first voltage being based on an initial pull-up control code;
• generating a pull-up control code for driving the first node based on the first reference voltage code;
• generating a second reference voltage code based on the voltage level of the selected reference voltage becoming the same as a second voltage of a second node, the second voltage being based on the pull-up control code;
• and
• generating a pull-down control code for driving the second node based on the second reference voltage code,
• wherein the impedance calibration circuit includes
• a calibration controller configured to receive the impedance calibration command and generate a calibration enable signal based on the impedance calibration command;
• an oscillator configured to generate a clock signal in response to the calibration enable signal;
• and
• a calibration circuit connected to the external resistor through the impedance pad, the calibration circuit configured to perform the impedance calibration operation in response to the calibration enable signal,
• wherein the calibration circuit includes
• a pull-up driver coupled between a power supply voltage and the first node, the pull-up driver configured to drive the first node with the first voltage based on the initial pull-up control code;
• a first comparator circuit configured to generate a first comparison signal by comparing the first voltage with the selected reference voltage;
• a reference voltage generator configured to generate a plurality of reference voltages;
• a replica pull-up driver coupled between the power supply voltage and the second node, the replica pull-up driver configured to drive the second node with the second voltage based on the pull-up control code;
• a pull-down driver coupled between the second node and a ground voltage;
• a second comparator circuit configured to generate a second comparison signal by comparing the second voltage with the selected reference voltage;
• and
• a control/code generation circuit configured to
• select the selected reference voltage from among the plurality of reference voltages;
• generate the first reference voltage code based on the first comparison signal;
• generate the pull-up control code based on the first reference voltage code;
• generate the second reference voltage code based on the second comparison signal;
• generate the pull-down control code based on the second reference voltage code;
• and
• provide the pull-down control code to the pull-down driver,
• wherein the control/code generation circuit includes
• a selection signal generator configured to generate selection signals and inverted selection signals based on the clock signal, and
• a reference voltage selector configured to output the selected reference voltage by selecting at least a portion of the plurality of reference voltages based on the selection signals and the inverted selection signals during each of a plurality of cycles.

An impedance calibration circuit, comprising:

• a calibration controller configured to receive an impedance calibration command and generate a calibration enable signal based on the impedance calibration command;
• an oscillator configured to generate a clock signal in response to the calibration enable signal;
• and
• a calibration circuit connected to an external resistor provided in a board through an impedance pad, the calibration circuit, in response to the calibration enable signal, configured to:
• generate a first reference voltage code based on a voltage level of a selected reference voltage becoming the same as a first voltage of a first node coupled to the impedance pad, the first voltage being based on an initial pull-down control code;
• generate a pull-down control code for driving the first node based on the first reference voltage code;
• generate a second reference voltage code based on the voltage level of the selected reference voltage becoming the same as a second voltage of a second node, the second voltage being based on the pull-down control code;
• and
• generate a pull-up control code for driving the second node based on the second reference voltage code, and
• wherein the calibration circuit includes:
• a pull-down driver coupled between the first node and a ground voltage, the pull-down driver configured to drive the first node with the first voltage based on the initial pull-down control code;
• a first comparator circuit configured to generate a comparison signal by comparing the first voltage with the selected reference voltage;
• a reference voltage generator configured to generate a plurality of reference voltages;
• and
• a control/code generation circuit configured to:
• select the selected reference voltage from among the plurality of reference voltages;
• generate the first reference voltage code based on the first comparison signal;
• generate the pull-down control code based on the first reference voltage code;
• and
• provide the pull-down control code to the pull-down driver,
• wherein the control/code generation circuit includes
• a selection signal generator configured to generate selection signals and inverted selection signals based on the clock signal, and
• a reference voltage selector configured to output the selected reference voltage by selecting at least a portion of the plurality of reference voltages based on the selection signals and the inverted selection signals during each of a plurality of cycles.