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US 12,763,116 B2Granted
Non-volatile memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsSeungyeon Kim, Daeseok Byeon
Life of this patent
Estimating the term…
Abstract
A non-volatile memory device includes a first semiconductor layer including a first cell region in which a first memory cell array is disposed, a second cell region in which a second memory cell array is disposed, wherein the first memory cell array and the second memory cell array each include a plurality of word lines, a plurality of memory cells, and a plurality of bit lines, and a second semiconductor layer including a page buffer circuit region in which a page buffer circuit connected to the first memory cell array and the second memory cell array is disposed, wherein the page buffer circuit region overlaps a boundary region between the first cell region and the second cell region when viewed from the vertical direction.
Claims20
A non-volatile memory device comprising:
- a first semiconductor layer comprising a first cell region in which a first memory cell array is disposed, a second cell region in which a second memory cell array is disposed, and a first metal pad layer, wherein the first memory cell array and the second memory cell array each comprise a plurality of word lines stacked in a vertical direction, a plurality of memory cells respectively connected to the plurality of word lines, and a plurality of bit lines;
- and
- a second semiconductor layer comprising a page buffer circuit region in which a page buffer circuit connected to the first memory cell array and the second memory cell array is disposed, and a second metal pad layer, wherein the second semiconductor layer is connected to the first semiconductor layer in the vertical direction through bonding by the first metal pad layer and the second metal pad layer,
- wherein the page buffer circuit includes at least one transistor that overlaps a boundary region within the first semiconductor layer between the first cell region and the second cell region when viewed from the vertical direction,
- wherein the page buffer circuit comprises, within the second semiconductor layer:
- a first switch connected between a page buffer and a first bit line connected to the first memory cell array;
- a second switch connected between the page buffer and a second bit line connected to the second memory cell array;
- and
- the page buffer comprising a sensing latch connected to the first switch and the second switch in common, and
- wherein at least one of the first switch, the second switch, and the page buffer overlaps the boundary region when viewed from the vertical direction.
7 more elements
A non-volatile memory device comprising:
- a first semiconductor layer comprising a first cell region in which a first memory cell array is disposed and a second cell region in which a second memory cell array is disposed, wherein the first memory cell array and the second memory cell array each comprises a plurality of word lines stacked in a vertical direction, a plurality of memory cells respectively connected to the plurality of word lines, and a plurality of bit lines, and wherein the first cell region is horizontally separated from the second cell region by a boundary region disposed therebetween;
- and
- a second semiconductor layer disposed under the first semiconductor layer and comprising a page buffer circuit region in which a page buffer circuit connected to the first memory cell array and the second memory cell array is disposed,
- wherein the page buffer circuit includes a page buffer, a first switch connected between the page buffer and a first bit line of the first memory cell array and a second switch connected between the page buffer and a second bit line of the second memory cell array,
- wherein the page buffer comprises a sensing latch connected to the first switch and the second switch in common, and
- wherein the first switch and the second switch are located in a region of the second semiconductor layer that vertically overlaps the boundary region.
3 more elements
A non-volatile memory device comprising:
- a first memory cell array comprising a plurality of word lines and a plurality of first bit lines;
- a second memory cell array comprising a plurality of word lines and a plurality of second bit lines, the second memory cell array horizontally separated from the first memory cell array by a boundary region disposed therebetween;
- and
- a page buffer circuit shared by the first memory cell array and the second memory cell array,
- wherein the page buffer circuit comprises:
- a first switch connected between a page buffer and a first bit line of the first memory cell array;
- a second switch connected between the page buffer and a second bit line of the second memory cell array;
- and
- the page buffer comprising a sensing latch connected to the first switch and the second switch in common,
- wherein at least one of the first switch and the second switch is below and vertically overlaps the boundary region.
7 more elements
Dependencies are inferred from the claim text.