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US 12,763,115 B2Granted
Transceiver for data or signal transmission and a memory system including the transceiver
AssigneeSK hynix Inc.
InventorsJun Seo Jang, Sung Hwa Ok, Eun Ji Choi, Jae Hyeong Hong
Life of this patent
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Abstract
A transceiver includes a first inverter chain configured to deliver a signal in response to an enable signal and a second inverter chain which is coupled to the first inverter chain in parallel and configured to output a reset value of the signal in response to an inverted enable signal.
Claims20
A transceiver comprising:
- a first inverter chain configured to deliver a signal in response to an enable signal;
- and
- a second inverter chain coupled to the first inverter chain in parallel and configured to output a reset value of the signal in response to an inverted enable signal,
- wherein only one of the first inverter chain or the second inverter chain operates exclusively for delivering respectively the signal or the reset value of the signal based on the enable signal and the inverted enable signal.
1 more element
A memory system comprising:
- plural memory dies configured to store data;
- and
- a memory controller coupled to the plural memory dies via a common channel and configured to control the plural memory dies,
- wherein at least one of the plural memory dies and the controller comprises a transceiver comprising:
- a first inverter chain configured to deliver a signal in response to an enable signal;
- and
- a second inverter chain coupled to the first inverter chain in parallel and configured to output a reset value of the signal in response to an inverted enable signal, and
- wherein only one of the first inverter chain or the second inverter chain operates exclusively for delivering respectively the signal or the reset value of the signal based on the enable signal and the inverted enable signal.
5 more elements
Dependencies are inferred from the claim text.