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US 12,763,114 B2Granted
Circuit with a low-power charge-sharing light-sleep mode
AssigneeQUALCOMM Incorproated
InventorsChi-Jui Chen, Xiao Chen, Sonia Ghosh, Hochul Lee, Anil Chowdary Kota, Giby Samson
Life of this patent
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Abstract
A circuit is provided with a selectively diode-connected head switch transistor. During a light-sleep mode, the head switch transistor is diode connected so that a power supply voltage passing through the diode-connected head switch transistor is reduced by a transistor threshold voltage drop. During an active mode, the diode connection is opened so that the head switch transistor passes a power supply voltage with virtually no voltage drop.
Claims14
A memory, comprising:
- a bitcell array having a first power supply node for receiving a bitcell array power supply voltage;
- a voltage rail for a memory power supply voltage;
- a first transistor having a first terminal coupled to the voltage rail and a second terminal coupled to the first power supply node;
- a second transistor having a first terminal coupled to a gate of the first transistor and having a second terminal coupled to the first power supply node;
- a first node for a light-sleep mode signal, wherein the first node is coupled to a gate of the second transistor;
- a memory periphery having a second power supply node for receiving a memory periphery power supply voltage;
- a third transistor having a first terminal coupled to the voltage rail and having a second terminal coupled to the second power supply node;
- and
- a fourth transistor having a first terminal coupled to the second power supply node, a second terminal coupled to the first power supply node, and a gate coupled to the first node, wherein a size of the fourth transistor is less than a size of the first transistor.
6 more elements
An integrated circuit, comprising:
- a voltage rail for a power supply voltage;
- a circuit having a power supply node;
- and
- a head switch transistor coupled between the voltage rail and the power supply node, wherein the at least one head switch transistor is configured into a diode-connected state during a light-sleep mode for the circuit and is configured into a non-diode-connected state during an active mode for the circuit;
- a first node for a deep-sleep mode signal;
- a switch coupled between the first node for the deep-sleep mode signal and a gate of the head switch transistor, wherein the switch is configured to open during the light-sleep mode for the circuit and to close during a deep-sleep mode for the circuit and during an active mode for the circuit;
- and
- a first inverter having an input terminal coupled to a second node for a deep-sleep mode input signal and having an output terminal coupled to the first node for the deep-sleep mode signal.
5 more elements
Dependencies are inferred from the claim text.