Semiconductor device and data storage system including the same

A semiconductor device, comprising:

• a first structure having a first side surface and a second side surface opposing each other, and including a first connection region, a first memory cell array region, a second connection region, a third connection region, a second memory cell array region, and a fourth connection region sequentially arranged from the first side surface in a first direction toward the second side surface;
• and
• a second structure including a peripheral circuit and overlapping the first structure,
• wherein the first structure includes:
• first-side conductive layers disposed in the first connection region, the first memory cell array region, and the second connection region, the first-side conductive layers extending from the first connection region to the second connection region passing through the first memory cell array region;
• a first vertical memory structure penetrating the first-side conductive layers in the first memory cell array region;
• second-side conductive layers disposed in the third connection region, the second memory cell array region, and the fourth connection region, wherein the second-side conductive layers extending from the third connection region to the fourth connection region passing through the second memory cell array region;
• and
• a second vertical memory structure penetrating the second-side conductive layers in the second memory cell array region,
• wherein the first-side conductive layers include:
• a first lower conductive group having first lower pads that are arranged in a staircase shape in the second connection region;
• and
• a first upper conductive group disposed on a level higher than a level of the first lower conductive group and having first upper pads that are arranged in a staircase shape in the first connection region,
• wherein the second-side conductive layers include:
• a second lower conductive group disposed at a same level as the first lower conductive group and having second lower pads that are arranged in a staircase shape in the third connection region;
• and
• a second upper conductive group disposed at a same level as the first upper conductive group and having second upper pads that are arranged in a staircase shape in the fourth connection region.

A data storage system, comprising:

• a semiconductor device including an input/output pad;
• and
• a controller electrically connected to the semiconductor device through the input/output pad and controlling the semiconductor device,
• wherein the semiconductor device includes:
• a first structure having a first side surface and a second side surface opposing each other, and including a first memory block and a second memory block sequentially arranged in a first direction;
• and
• a second structure including a peripheral circuit and overlapping the first structure,
• wherein the first memory block has a first connection region, a first memory cell array region, and a second connection region sequentially arranged in the first direction,
• wherein the second memory block has a third connection region, a second memory cell array region, and a fourth connection region sequentially arranged in the first direction,
• wherein the first memory block includes first gate electrodes that are spaced apart from each other in a vertical direction and extend from the first connection region to the second connection region passing through the first memory cell array region,
• wherein the second memory block includes second gate electrodes that are spaced apart from each other in the vertical direction and extend from the third connection region to the fourth connection region passing through the second memory cell array region,
• wherein the first gate electrodes of the first memory block include:
• first word lines having first word line pads that are disposed in the second connection region;
• and
• a first upper gate line having a first upper gate pad that is disposed in the first connection region and disposed on the first word lines,
• wherein the second gate electrodes of the second memory block includes:
• a second word lines having second word line pads that are disposed in the third connection region;
• and
• a second upper gate line having a second upper gate pad that is disposed in the fourth connection region and disposed on the second word lines,
• wherein the first structure includes:
• first word line contact plugs connected to the first word line pads;
• a first upper gate contact plug connected to the first upper gate pad;
• second word line contact plugs connected to the second word line pads;
• and
• a second upper gate contact plug connected to the second upper gate pad.