Logic die-based techniques for DRAM row segmentation and fine-grained accesses on stacked memory
AssigneeAdvanced Micro Devices, Inc.
InventorsVignesh Adhinarayanan, Hyung-Dong Lee, Bradford Beckmann, Seyedmohammad Seyedzadehdelcheh, Sergey Blagodurov
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Abstract
Integrated circuit (IC) memory devices and methods for fabricating the same are provided. In one example, an integrated circuit (IC) memory device is provided that includes a substrate, at least two or more memory (IC) dies, and a non-memory IC die integrated in a chip package. The memory (IC) dies are stacked on the substrate to form a memory die stack. The non-memory IC die contains row segmentation logic having an output routed to corresponding wordline drivers of the memory IC dies through vertical wiring passing through the memory die stack.
Claims19
An integrated circuit (IC) memory device, comprising:
- at least two or more memory IC dies stacked form a memory die stack, wherein a first memory IC die of the two or more memory IC dies further comprises a plurality of memory mats arranged in a common row, each memory mat having a local sub-wordline driver coupled thereto;
- and
- a non-memory IC die containing in-die logic circuitry having an output routed to circuitry of the memory IC dies through vertical wiring passing through the memory die stack, the in-die logic circuitry comprising row segmentation logic circuitry, wherein the row segmentation logic circuitry is disposed in the non-memory IC die and coupled to the local sub-wordline drivers by individual routing extending between the row segmentation logic circuitry and the local sub-wordline segment drivers across a hybrid bond, the row segmentation logic circuitry configured to select separate groups of the local sub-wordline drivers coupled to the memory mats within the common row.
An integrated circuit (IC) memory device, comprising:
- at least two or more memory IC dies stacked form a memory die stack, wherein a first memory IC die of the two or more memory IC dies further comprises a row of memory mats;
- and
- a non-memory IC die containing in-die logic circuitry having an output routed to circuitry of the memory IC dies through vertical wiring passing through the memory die stack, the in-die logic circuitry comprising row segmentation logic circuitry, plurality of sense amplifiers, row select logic circuitry, and column select logic circuitry, wherein the row segmentation logic circuitry of the non-memory IC die is configured to select one or more mats from the row of mats coupled to a common word line within the first memory IC die.
An integrated circuit (IC) memory device, comprising:
- a substrate;
- at least two or more memory IC dies stacked on the substrate to form a memory die stack, wherein a first memory IC die of the two or more memory IC dies further comprises a row of memory mats, each row comprising two or more memory mats, each memory mat having at least one corresponding wordline driver;
- and
- a non-memory IC die containing row segmentation logic circuitry having routing uniquely coupled to corresponding wordline drivers of the memory IC dies through vertical wiring passing through the memory die stack.
A method for operating a memory device, the method comprising:
- transmitting, from a row decoder circuitry located in a non-memory IC die to a memory IC die stacked therewith, a signal causing a portion of memory grains arranged within the memory IC die in a common row and coupled to a common word line to be selected;
- and
- reading bits from the selected portion of memory grains.
Dependencies are inferred from the claim text.