# US 12,763,033 B2 · Display module and electronic device including the display module

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- Number: US 12,763,033 B2
- Document ID: US12763033B2
- Status: Granted
- Kind: B2
- Application number: 19/350,023
- Filed: 2025-10-05
- Published: 2026-08-06
- Granted: 2026-10-13
- Earliest claimed: 2025-02-05
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., LTD.
- Inventors: Sanghun Kim
- Web page: https://patentgrep.com/patent/US12763033B2

## CPC

- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0238: Improving the black level
- G09G 2330/021: Power management, e.g. power saving
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display module includes a plurality of pixels and a gate driving circuit. The gate driving circuit includes a plurality of stages electrically connected with the plurality of pixels. A first stage among the plurality of stages receives a high signal having a first potential, a low signal having a second potential lower than the first potential, and a first clock signal. The first stage includes a first charging unit, a first inverting unit, a first main boosting unit, a first main output unit, and a first sub-output unit. The first charging unit includes a first main capacitor disposed between a first upper charging node and a first lower charging node. The first inverting unit transfers the high signal to a first output node or electrically connects the first lower charging node to the first output node according to the first clock signal.

## Claims

### Claim 1

A display module comprising:
a plurality of pixels; and
a gate driving circuit,
wherein:
the gate driving circuit comprises a plurality of stages electrically connected with the plurality of pixels,
a first stage among the plurality of stages receives a high signal having a first potential, a low signal having a second potential lower than the first potential, and a first clock signal,
the first stage comprises:
a first charging unit comprising a first main capacitor disposed between a first upper charging node and a first lower charging node;
a first inverting unit which transfers the high signal to a first output node or electrically connects the first lower charging node to the first output node based on the first clock signal;
a first main boosting unit which transfers the low signal to the first upper charging node in accordance with a potential of the first output node;
a first main output unit which provides a first non-inverted output signal to at least one of the plurality of pixels based on the potential of the first output node; and
a first sub-output unit which provides a first inverted output signal to at least one of the plurality of pixels in accordance with the potential of the first output node and the potential of the first non-inverted output signal, and
one of the first non-inverted output signal and the first inverted output signal is the high signal, and the other of the first non-inverted output signal and the first inverted output signal is the low signal.

### Claim 2 (depends on 1)

The display module of claim 1, wherein:
the first charging unit charges the first main capacitor with a charge amount corresponding to a potential difference between the high signal and the low signal in response to one of an initialization signal and a carry signal and the first clock signal, and
the carry signal is an electrical signal received from a stage other than the first stage among the plurality of stages.

### Claim 3 (depends on 1)

The display module of claim 1, wherein:
the first main output unit comprises a first upper main output transistor and a first lower main output transistor,
one of the first upper main output transistor and the first lower main output transistor turns on while the other of the first upper main output transistor and the first lower main output transistor turns off, based on the potential of the first output node,
the first sub-output unit comprises a first upper sub-output transistor and a first lower sub-output transistor, and
the first upper sub-output transistor is controlled by the potential of the first non-inverted output signal and provides the high signal as the first inverted output signal based on the potential of the first non-inverted output signal, and the first lower sub-output transistor is controlled by the potential of the first output node and provides the low signal as the first inverted output signal based on the potential of the first output node.

### Claim 4 (depends on 1)

The display module of claim 1, wherein:
a second stage among the plurality of stages receives the high signal, the low signal, and a second clock signal, and
the second stage comprises:
a second charging unit comprising a second main capacitor disposed between a second upper charging node and a second lower charging node;
a second inverting unit which transfers the high signal to a second output node or electrically connects the second lower charging node to the second output node based on the second clock signal;
a second main boosting unit which transfers the low signal to the second upper charging node based on the potential of the second output node;
a second main output unit which provides a second non-inverted output signal to at least one of the plurality of pixels based on the potential of the second output node; and
a second sub-output unit which provides a second inverted output signal to at least one of the plurality of pixels based on the potential of the second output node and the potential of the second non-inverted output signal, wherein one of the second non-inverted output signal and the second inverted output signal is the high signal, and the other of the second non-inverted output signal and the second inverted output signal is the low signal,
wherein:
the first stage further comprises a first main initialization unit, and
the first main initialization unit provides the high signal to the first lower charging node based on one of the second non-inverted output signal and the second inverted output signal.

### Claim 5 (depends on 4)

The display module of claim 4, wherein the first clock signal and the second clock signal have different phases with respect to one another.

### Claim 6 (depends on 1)

The display module of claim 1, wherein:
the first stage is further provided with a stage initialization signal, and
the first stage further comprises a first sub-initialization unit which transfers the high signal to the first lower charging node based on the stage initialization signal.

### Claim 7 (depends on 1)

The display module of claim 1, wherein:
the first clock signal is an electrical signal which swings between the first potential and the second potential, and
a duration for which the potential of the first clock signal is maintained at the first potential is shorter than a duration for which the potential of the first clock signal is maintained at the second potential.

### Claim 8 (depends on 1)

The display module of claim 1, wherein:
the first stage further comprises a first sub-boosting unit comprising a first sub-capacitor, the first sub-capacitor is disposed between the first upper charging node and a first sub-boosting node, and
the first sub-boosting node is electrically connected with the first inverting unit,
wherein the first sub-capacitor is charged or the first sub-boosting node is electrically connected to the first output node according to the first clock signal.

### Claim 9

A display module comprising:
a plurality of pixels; and
a gate driving circuit,
wherein:
the gate driving circuit comprises a plurality of stages electrically connected with the plurality of pixels, and
a first stage among the plurality of stages comprises:
a first upper output terminal which transfers a first non-inverted output signal to at least one of the plurality of pixels;
a first carry terminal electrically connected to a first upper charging node and a second stage among the plurality of stages;
a first high-potential terminal configured to receive a high signal having a first potential;
a first low-potential terminal configured to receive a low signal having a second potential lower than the first potential;
a first clock terminal configured to receive a first clock signal;
a first input terminal configured to receive one of an initialization signal and a carry signal, wherein the carry signal is an electrical signal received from a stage other than the first stage among the plurality of stages;
a first upper input transistor disposed between the first high-potential terminal and the first upper charging node and which turns on or turns off in response to the first clock signal;
a first lower input transistor disposed between a first lower charging node insulated from the first upper charging node and the first low-potential terminal and which turns on or turns off based on a potential of the first input terminal;
a first main capacitor disposed between the first upper input transistor and the first lower input transistor;
a first lower inverting transistor disposed between the first lower charging node and a first output node and which turns on or turns off based on a potential of the first clock terminal;
a first upper inverting transistor disposed between the first lower inverting transistor and the first high-potential terminal and which turns on or turns off based on a potential of the first clock terminal;
a first main boosting transistor disposed between the first low-potential terminal and the first upper charging node and which turns on or turns off based on a potential of the first output node;
a first upper main output transistor disposed between the first high-potential terminal and the first upper output terminal and which turns on or turns off based on a potential of the first output node; and
a first lower main output transistor disposed between the first low-potential terminal and the first upper output terminal and which turns on or turns off based on a potential of the first output node.

### Claim 10 (depends on 9)

The display module of claim 9, further comprising:
a first lower output terminal which transfers a first inverted output signal to at least one of the plurality of pixels;
a first upper sub-output transistor disposed between the first high-potential terminal and the first lower output terminal and which turns on or turns off based on a potential of the first non-inverted output signal; and
a first lower sub-output transistor disposed between the first low-potential terminal and the first lower output terminal and which turns on or turns off based on a potential of the first output node.

### Claim 11 (depends on 9)

The display module of claim 9, wherein:
one of the first upper main output transistor and the first lower main output transistor is an N-type metal-oxide-semiconductor (NMOS) transistor, and
the other of the first upper main output transistor and the first lower main output transistor is a P-type metal-oxide-semiconductor (PMOS) transistor.

### Claim 12 (depends on 9)

The display module of claim 9, wherein:
the first upper main output transistor and the first lower main output transistor are controlled such that one of the first upper main output transistor and the first lower main output transistor turns on and the other the first upper main output transistor and the first lower main output transistor turns off based on a potential of the first output node, and
one of the first non-inverted output signal and a first inverted output signal is the high signal and the other of the first non-inverted output signal and the first inverted output signal is the low signal.

### Claim 13 (depends on 12)

The display module of claim 12, wherein the second stage comprises:
a second upper output terminal which transfers a second non-inverted output signal to at least one of the plurality of pixels;
a second lower output terminal which transfers a second inverted output signal to at least one of the plurality of pixels;
a second high-potential terminal configured to receive the high signal;
a second low-potential terminal configured to receive the low signal;
a second clock terminal configured to receive a second clock signal;
a second input terminal electrically connected with the first carry terminal of the first stage;
a second upper input transistor disposed between the second high-potential terminal and a second upper charging node and which turns on or turns off in response to the second clock signal;
a second lower input transistor disposed between a second lower charging node insulated from the second upper charging node and the second low-potential terminal and which turns on or turns off based on a potential of the second input terminal;
a second main capacitor disposed between the second upper input transistor and the second lower input transistor;
a second lower inverting transistor disposed between the second lower charging node and a second output node and which turns on or turns off based on a potential of the second clock terminal;
a second upper inverting transistor disposed between the second lower inverting transistor and the second high-potential terminal and which turns on or turns off based on a potential of the second clock terminal;
a second main boosting transistor disposed between the second low-potential terminal and the second upper charging node and which turns on or turns off based on a potential of the second output node;
a second upper main output transistor disposed between the second high-potential terminal and the second upper output terminal and which turns on or turns off based on a potential of the second output node;
a second lower main output transistor disposed between the second low-potential terminal and the second upper output terminal and which turns on or turns off based on a potential of the second output node;
a second upper sub-output transistor disposed between the second high-potential terminal and the second lower output terminal and which turns on or turns off based on a potential of the second non-inverted output signal; and
a second lower sub-output transistor disposed between the second low-potential terminal and the second lower output terminal and which turns on or turns off based on a potential of the second output node,
wherein the first stage further comprises:
a first main initialization terminal electrically connected to one of the second upper output terminal and the second lower output terminal; and
a first main initialization transistor disposed between the first lower charging node and the first high-potential terminal and which turns on or turns off based on a potential of the first main initialization terminal.

### Claim 14 (depends on 13)

The display module of claim 13, wherein the first clock signal and the second clock signal have different phases with respect to one another.

### Claim 15 (depends on 13)

The display module of claim 13, wherein:
the first clock signal is an electrical signal which swings between the first potential and the second potential, and a duration for which the potential of the first clock signal is maintained at the first potential is shorter than a duration for which the potential of the first clock signal is maintained at the second potential, and
the second clock signal is an electrical signal which swings between the first potential and the second potential, and a duration for which the potential of the second clock signal is maintained at the first potential is shorter than a duration for which the potential of the second clock signal is maintained at the second potential.

### Claim 16 (depends on 13)

The display module of claim 13, wherein the first stage further comprises:
a first sub-initialization terminal configured to receive a stage initialization signal; and
a first sub-initialization transistor disposed between the first lower charging node and the first high-potential terminal and which turns on or turns off based on a potential of the first sub-initialization terminal.

### Claim 17 (depends on 16)

The display module of claim 16, wherein the first stage further comprises a first sub-capacitor disposed between the first upper charging node and the first upper inverting transistor.

### Claim 18

An electronic device comprising:
a display module configured to emit light;
a processor configured to control the display module;
a memory having data for operation of the display module or the processor stored therein; and
a power module configured to generate or supply power,
wherein:
the display module comprises a plurality of pixels and a gate driving circuit,
the gate driving circuit comprises a plurality of stages electrically connected with the plurality of pixels,
a first stage among the plurality of stages receives a high signal having a first potential, a low signal having a second potential lower than the first potential, and a first clock signal,
the first stage comprises:
a first charging unit comprising a first main capacitor disposed between a first upper charging node and a first lower charging node;
a first inverting unit which transfers the high signal to a first output node or electrically connects the first lower charging node to the first output node in response to the first clock signal;
a first main boosting unit which transfers the low signal to the first upper charging node based on a potential of the first output node;
a first main output unit which provides a first non-inverted output signal to at least one of the plurality of pixels based on a potential of the first output node; and
a first sub-output unit which provides a first inverted output signal to at least one of the plurality of pixels based on a potential of the first output node and a potential of the first non-inverted output signal, and
one of the first non-inverted output signal and the first inverted output signal is the high signal, and the other of the first non-inverted output signal and the first inverted output signal is the low signal.

### Claim 19 (depends on 18)

The electronic device of claim 18, wherein:
the first main output unit comprises a first upper main output transistor and a first lower main output transistor,
the first upper main output transistor and the first lower main output transistor are controlled such that one of the first upper main output transistor and the first lower main output transistor turns on and the other of the first upper main output transistor and the first lower main output transistor turns off based on a potential of the first output node,
the first sub-output unit comprises a first upper sub-output transistor and a first lower sub-output transistor,
the first upper sub-output transistor is controlled to provide the high signal as the first inverted output signal based on a potential of the first non-inverted output signal, and
the first lower sub-output transistor is controlled to provide the low signal as the first inverted output signal based on a potential of the first output node.

### Claim 20 (depends on 19)

The electronic device of claim 19, wherein:
the first stage further comprises a first sub-boosting unit comprising a first sub-capacitor,
the first sub-capacitor is disposed between the first upper charging node and a first sub-boosting node, and the first sub-boosting node is electrically connected to the first inverting unit, and
the first sub-capacitor is charged or the first sub-boosting node is electrically connected to the first output node according to the first clock signal.