Display device, and electronic device including the same

A display device, comprising:

• pixels connected with scan lines, light emitting control lines, and data lines;
• and
• a scan driver for driving the scan lines,
• wherein any one of the pixels comprises:
• a first transistor, which has a gate electrode connected to a first node and is connected between a second node and a first drive power node to which a first drive power is supplied;
• a second transistor connected between a data line and the first node and having a gate electrode electrically connected to a first scan line of the scan lines;
• a third transistor connected between a reference power node, to which a reference power is supplied, and the first node and having a gate electrode electrically connected to a second scan line of the scan lines;
• a fourth transistor connected between an initialization power node, to which an initialization power is supplied, and a third node and having a gate electrode electrically connected to a third scan line of the scan lines;
• a fifth transistor connected between the first drive power node and the first transistor and having a gate electrode electrically connected to a first light emitting control line of the light emitting control lines;
• a sixth transistor connected between the second node and the third node and having a gate electrode electrically connected to a second light emitting control line of the light emitting control lines;
• and
• a light emitting element connected to the third node, p1 wherein the fourth transistor, the fifth transistor, and the sixth transistor are N-type low-temperature poly-silicon (LTPS) transistors.

A display device comprising:

• pixels connected with scan lines, light emitting control lines, and data lines;
• and
• a scan driver for driving the scan lines,
• wherein the scan driver comprises stage circuits, which are connected with the scan lines,
• wherein any one of the stage circuits comprises:
• first transistors connected in series between an input terminal and a first node and having gate electrodes connected to a first clock terminal to which a first clock signal is supplied;
• second and third transistors connected in series between a second power terminal, to which a second power is supplied, and the first node;
• a fourth transistor connected between the first clock terminal and a second node and having a gate electrode connected to the first node;
• a fifth transistor connected between a first power terminal, to which a first power is supplied, and the second node and having a gate electrode connected to the first clock terminal;
• a sixth transistor connected between the first node and a third node and having a gate electrode connected to the first power terminal;
• a seventh transistor connected between a second clock terminal, to which a second clock signal is supplied, and an output terminal and having a gate electrode connected to the third node;
• and
• an eighth transistor connected between the output terminal and the second power terminal and having a gate electrode connected to the second node.