Pixel driving circuit, driving method thereof and display panel

A pixel driving circuit, comprising:

• a driving circuit and an initialization circuit;
• wherein the driving circuit is connected to a first node, a second node, and a third node;
• wherein the initialization circuit is connected to the first node, the initialization circuit is further connected to the second node and/or the third node, and the initialization circuit is configured to provide a first initialization voltage to the first node, provide a first reset voltage to the second node and/or provide a second reset voltage to the third node, so as to control a driving transistor in the driving circuit to be turned on;
• wherein a voltage difference between the first node and the third node is greater than a threshold voltage of the driving transistor, and a voltage difference between the first node and the second node is less than the threshold voltage of the driving transistor;
• the pixel driving circuit further comprises a data writing circuit, and a control electrode of the data writing circuit is connected to a gate driving signal terminal;
• the pixel driving circuit further comprises a third reset circuit, and a control electrode of the third reset circuit is connected to a first reset control signal line;
• a control electrode of a first reset circuit of the initialization circuit is connected to a second reset control signal line;
• during a time period of each frame, both a first time period in which the second reset control signal line provides a turn-on level signal and a second time period in which the gate driving signal terminal provides a turn-on level signal are within a third time period in which the first reset control signal line provides a turn-on level signal, wherein the first reset control signal line provides the turn-on level signal during the entirety of the third time period;
• the pixel driving circuit further comprises a threshold compensation circuit;
• wherein the data writing circuit is connected to a first preset node, a data signal terminal and the gate driving signal terminal, and configured to write a data voltage provided by the data signal terminal to the first preset node in response to control of a signal of the gate driving signal terminal;
• wherein the threshold compensation circuit is connected to a second preset node, the first node and the gate driving signal terminal, and configured to connect the second preset node to the first node in response to the control of the signal of the gate driving signal terminal;
• wherein one of the first preset node and the second preset node is the second node, and the other of the first preset node and the second preset node is the third node;
• wherein the initialization circuit comprises the first reset circuit;
• the first reset circuit is connected to a first control signal terminal, the first node, and a first voltage supply terminal, and configured to transmit the first initialization voltage provided from the first voltage supply terminal to the first node in response to control of a signal of the first control signal terminal;
• the initialization circuit further comprises a second reset circuit and/or a fourth reset circuit;
• the second reset circuit is connected to a second control signal terminal, the second node, and a second voltage supply terminal, and is configured to transmit the first reset voltage provided from the second voltage supply terminal to the second node in response to control of a signal of the second control signal terminal;
• the fourth reset circuit is connected to a third control signal terminal, the third node, and a third voltage supply terminal, and is configured to transmit the second reset voltage provided from the third voltage supply terminal to the third node in response to control of a signal of the third control signal terminal;
• wherein the first voltage supply terminal is connected to a first initialization voltage supply line, and the first control signal terminal is connected to the second reset control signal line;
• in a case where the initialization circuit comprises the second reset circuit, the second voltage supply terminal is connected to a first reset voltage supply line, and the second control signal terminal is connected to the second reset control signal line;
• and
• in a case where the initialization circuit comprises the fourth reset circuit, the third voltage supply terminal is connected to a second reset voltage supply line, and the third control signal terminal is connected to the second reset control signal line.