Timing controller and display device including the same

A display device comprising:

• a plurality of pixels connected to a plurality of gate lines;
• a gate driver that supplies a plurality of gate signals to the plurality of pixels through the plurality of gate lines;
• a plurality of gate pads that transmit a plurality of control signals to the gate driver through a plurality of control lines;
• and
• a timing controller that supplies the plurality of control signals to the plurality of gate pads,
• wherein the timing controller comprises:
• a control signal generator that generates the plurality of control signals;
• an output pad unit including a plurality of output pads for outputting the plurality of control signals to an outside of the timing controller;
• and
• a plurality of transmission lines connecting the output pad unit to the control signal generator,
• wherein the plurality of output pads are grouped into a plurality of sub pad groups and each of the plurality of sub pad groups includes P output pads,
• wherein P represents a number of output pads in each of the plurality of sub pad groups and the P output pads are electrically connected in series with each other,
• wherein the P output pads are adjacent to each other in a first direction, and the output pad unit is spaced apart from the control signal generator in a second direction crossing the first direction.

An electronic device comprising a processor and a timing controller the timing controller comprising:

• a control signal generator that supplies a plurality of control signals;
• an output pad unit including a plurality of output pads grouped into a plurality of sub pad groups for outputting the plurality of control signals to an outside of the timing controller;
• and
• a plurality of transmission lines, each of the plurality of transmission lines connecting a corresponding one of the plurality of sub pad groups to the control signal generator,
• wherein the plurality of sub pad groups are arranged in a plurality of rows and a plurality of columns and each of the plurality of sub pad groups includes P output pads,
• wherein P represents a number of output pads in each of the plurality of sub pad groups and the P output pads are electrically connected in series with each other,
• wherein the P output pads are adjacent to each other in a first direction, and the output pad unit is spaced apart from the control signal generator in a second direction crossing the first direction,
• wherein each of the plurality of rows extends in the first direction, and the plurality of rows are spaced apart from each other in the second direction, and
• wherein each of the plurality of columns extend in the second direction, and the plurality of columns are spaced apart from each other in the first direction.