Ferroelectric memory device and electronic device including the same

A neural network device comprising:

• a plurality of word lines;
• a plurality of bit lines intersecting the plurality of word lines;
• a plurality of input lines;
• a plurality of output lines;
• a plurality of synaptic elements at intersections between the plurality of word lines and the plurality of bit lines, and each of the plurality of synaptic elements being electrically connected to a corresponding one of the plurality of word lines, a corresponding one of the plurality of bit lines, a corresponding one of the plurality of input lines, and a corresponding one of the plurality of output lines, a word line driver configured to apply a signal to the plurality of word lines;
• a bit line driver configured to apply a signal to the plurality of bit lines;
• an input circuit configured to apply a signal to the plurality of input lines;
• and
• an output circuit configured to output a signal from the plurality of output lines,
• wherein each of the plurality of synaptic elements comprises a ferroelectric memory cell,
• wherein the ferroelectric memory cell comprises
• a source,
• a drain,
• a channel layer between the source and the drain and connected to the source and the drain,
• a first gate electrode on the channel layer,
• a second gate electrode on the channel layer and spaced apart from the first gate electrode,
• a ferroelectric layer located between the channel layer and the first gate electrode, and
• the ferroelectric layer is between the channel layer and the second gate electrode, and
• an insulating layer between the ferroelectric layer and the channel layer, the insulating layer being in direct contact with the ferroelectric layer;
• wherein
• the word line driver and the bit line driver are configured to apply a pulse voltage to any one of the first gate electrode and the second gate electrode and configured to apply a direct current (DC) voltage or a different type of pulse voltage from the pulse voltage to an other of the first gate electrode and the second gate electrode.

An operating method of a ferroelectric memory device, the ferroelectric memory device comprising a source;

• a drain;
• a channel layer between the source and the drain, the channel layer connected to the source and the drain;
• a first gate electrode on the channel layer;
• a second gate electrode on the channel layer and spaced apart from the first gate electrode;
• a ferroelectric layer, the ferroelectric layer between the channel layer and the first gate electrode, and the ferroelectric layer being between the channel layer and the second gate electrode;
• and an insulating layer between the ferroelectric layer and the channel layer, the insulating layer being in direct contact with the ferroelectric layer, the method comprising:
• applying a pulse voltage to any one of the first gate electrode and the second gate electrode, and
• applying a direct current (DC) voltage or a different type of pulse voltage from the pulse voltage to other of the first gate electrode and the second gate electrode.