Semiconductor device including overpass-type channel

A synaptic array comprising:

• first to fourth semiconductor devices arranged in an array,
• each of the first to fourth semiconductor devices includes a first gate including a fin having a preset height, a charge storage layer formed on the first gate and the fin, a channel layer formed on a part of the charge storage layer and configured to overpass the fin of the first gate, a gate insulating layer formed on the channel layer, and a second gate formed on the gate insulating layer and configured to extend in a direction parallel to an overpassing direction of the channel layer, the fin protrudes in a height direction from a center of the first gate,
• one second gate line connecting the second gate of the first semiconductor device to the second gate of the second semiconductor device;
• another second gate line connecting the second gate of the third semiconductor device to the second gate of the fourth semiconductor device;
• one drain line shared by the first semiconductor device and the second semiconductor device;
• another drain line shared by the third semiconductor device and the fourth semiconductor device;
• one first gate line connecting the first gate of the first semiconductor device to the first gate of the third semiconductor device;
• another first gate line connecting the first gate of the second semiconductor device to the first gate of the fourth semiconductor device;
• one source line shared by the first semiconductor device and the third semiconductor device;
• and
• another source line shared by the second semiconductor device and the fourth semiconductor device,
• wherein an event-driven operation of simultaneously receiving an input signal to the second gate lines and the drain lines and outputting an output signal from the first and second source lines is enabled.