Artificial intelligence accelerator, artificial intelligence acceleration device, artificial intelligence acceleration chip, and data processing method

A data processing method, performed by an artificial intelligence accelerator comprising a control unit, a computing engine, a group control unit, and a group cache unit and the artificial intelligence accelerator being executed on a hardware platform including at least one of a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), the data processing method comprising:

• parsing, by using the control unit, a processing instruction for a target network layer in a neural network model to obtain a concurrent instruction, an input data set of the target network layer comprising a plurality of input tiles, and a depth of an input tile being obtained by performing adaptation processing according to a second quantity, the second quantity being an amount of processing data in each sliding window in a depth direction each time parallel processing is performed, and the adaptation processing being such that, in the depth direction, the input data set is adapted to the plurality of input tiles in which the second quantity of pieces of data are in one group;
• performing, by using the computing engine, parallel processing on a target input tile in the input data set according to the concurrent instruction to obtain target output data corresponding to the target input tile, wherein the computing engine comprises a plurality of processing elements, and each time the computing engine performs the parallel processing, a first quantity of the plurality of processing elements are invoked simultaneously, such that the artificial intelligence accelerator has a capability to respectively process data with a depth of the second quantity in parallel by simultaneously performing the first quantity of operation function;
• and
• storing by using the group control unit, by group, the target output data into the group cache unit that is provided with the first quantity of output caches, wherein the storing the target output data comprises storing, by group, the target output data into at least one output cache of the first quantity of output caches,
• wherein the target network layer has a first operation parallelism degree indicating a quantity of operation functions comprised in the target network layer,
• wherein the group control unit groups the input tiles in the input data set into a plurality of input data groups, each input data group comprising successively arranged input tiles, a number of which is determined based on the first operation parallelism degree and the first quantity, and
• wherein the computing engine performs offset filling processing on operation functions in the target network layer according to an arrangement position of the target input tile in a target input data group to which the target input tile belongs, to obtain a target filling function group;
• and invokes functions in the target filling function group according to the concurrent instruction to perform parallel processing on the target input tile.