Optimizing machine learning classification models for resource constraints in electronic design automation (EDA) computer aided design (CAD) flows

An integrated circuit (IC) device, comprising:

• smoothing circuitry configured to smooth a set of ordered discrete probabilistic classification scores to generate a set of smoothed ordered discrete probabilistic classification scores, wherein the set of ordered discrete probabilistic classification scores reflect machine-learning-generated probabilities that corresponding circuit design evaluation processes will detect a defect in a circuit design;
• change point detection circuitry configured to compute slope changes in the set of smoothed ordered discrete probabilistic classification scores and select a subset of the slope changes as bin boundaries based on a change-point threshold;
• binning circuitry configured to assign the circuit design evaluation processes to the bins based on values of the discrete probabilistic classification scores and the bin boundaries;
• and
• selection circuitry configured to select a subset of the circuit design evaluation processes from one or more of the bins, for evaluating the circuit design, based on metrics associated with the respective circuit design evaluation processes.

A method, comprising:

• adaptively binning an ordered set of discrete probabilistic classification scores based on slope changes in the ordered set of discrete probabilistic classification scores, wherein the discrete probabilistic classification scores reflect machine-learning-generated probabilities that corresponding circuit design evaluation processes will detect a defect in a circuit design;
• evaluating the bins consecutively, starting with a bin for which the assigned discrete probabilistic classification scores have the highest values, wherein the evaluating comprises, for each of the bins:
• computing a bin metric for the bin based on the metrics of the circuit design evaluation processes of the bin;
• selecting all of the circuit design evaluation processes of the bin if a sum of the bin metric and a tally of bin metrics of previously selected circuit design evaluation processes is below a selection threshold;
• and
• selecting a subset of the circuit design evaluation processes of the bin if the sum exceeds the selection threshold.