Systems and methods for automatic pin matching between functional blocks in a layout via a graphic-based layout editor

A computer-implemented method to support automatic pin matching in a circuit layout, comprising:

• presenting a plurality of blocks in the circuit layout on a display device to a user, wherein each of the blocks is placed within a set of boundaries in the circuit layout;
• recognizing a first action by the user to identify a first boundary of a reference block of the plurality of blocks;
• recognizing a second action by the user to identify a second boundary of a target block of the plurality of blocks;
• identifying a first set of pins on the first boundary of the reference block;
• identifying a second set of pins on the target block, wherein each of the pins in the second set of pins belongs to a same net as at least one of the pins in the first set of pins on the reference block;
• sorting the second set of pins on the target block to be in the same order as the first set of pins on the reference block based on their net ids;
• placing the sorted second set of pins on the identified second boundary of the target block;
• and
• connecting each pin in the first set of pins with a pin in the second set of pins that belongs to the same net via one or more interconnect wires.

A non-transitory computer readable storage medium having software instructions stored thereon that when executed cause a system to:

• present a plurality of blocks in the circuit layout on a display device to a user, wherein each of the blocks is placed within a set of boundaries in the circuit layout;
• recognize a first action by the user to identify a first boundary of a reference block of the plurality of blocks;
• recognize a second action by the user to identify a second boundary of a target block of the plurality of blocks;
• identify a first set of pins on the first boundary of the reference block;
• identify a second set of pins on the target block, wherein each of the pins in the second set of pins belongs to a same net as at least one of the pins in the first set of pins on the reference block;
• sort the second set of pins on the target block to be in the same order as the first set of pins on the reference block based on their net ids;
• place the sorted second set of pins on the identified second boundary of the target block;
• and
• connect each pin in the first set of pins with a pin in the second set of pins that belongs to the same net via one or more interconnect wires.