# US 12,762,241 B2 · System and method for storing system state data in a hardware register > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,762,241 B2 - Document ID: US12762241B2 - Status: Granted - Kind: B2 - Application number: 17/854,706 - Filed: 2022-06-30 - Published: 2023-07-27 - Granted: 2026-10-13 - Earliest claimed: 2022-01-27 - Assignees: Infineon Technologies Americas Corp. - Applicants: Cypress Semiconductor Corporation - Inventors: Jacek Dobaczewski - Web page: https://patentgrep.com/patent/US12762241B2 ## CPC - G06F 21/575: {Secure boot} - G06F 21/54: by adding security routines or objects to programs - G06F 21/554: {involving event detection and direct action} - G06F 21/577: {Assessing vulnerabilities and evaluating computer system security} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract One or more computing devices, systems, and/or methods are provided. In an example, a method comprises executing an application image to initialize a computing system. System state data associated with the initializing of the computing system is stored in a hardware register having at least one lockable until reset bit. A fault condition is identified responsive to the system state data not matching an expected value. ## Claims ### Claim 1 A system, comprising: a processor; a hardware register comprising at least a first lockable until reset bit and being addressable in a first address range; and a memory storing an application image comprising instructions, that when executed by the processor cause the processor to: store system state data having a first Hamming distance in the first lockable until reset bit of the hardware register during an initializing of the system; lock the first lockable until reset bit of the hardware register after storing the system state data in the first lockable until reset bit of the hardware register; store a system state verification parameter in the memory at a second address range different than the first address range; combine the system state data in the hardware register and the system state verification parameter to generate a combined system state verification parameter having a second Hamming distance greater than the first Hamming distance; and identify a fault condition responsive to the combined system state verification parameter not matching an expected value after completion of the initialization of the system. ### Claim 2 (depends on 1) The system of claim 1, wherein the system state data comprises life cycle state data. ### Claim 3 (depends on 1) The system of claim 1, wherein: the processor is to set the first lockable until reset bit of the hardware register after completion of a first phase of the initializing; and the processor is configured to set a second lockable until reset bit of the hardware register after completion of a second phase of the initializing. ### Claim 4 (depends on 1) The system of claim 1, wherein: the processor is configured to set the first lockable until reset bit of the hardware register responsive to a life cycle state of the system having a first value; the processor is configured to set a second lockable until reset bit of the hardware register responsive to the life cycle state having a second value; and the processor is configured to identify a fault condition responsive to more than one bit being set in the hardware register after completion of the initialization of the system. ### Claim 5 (depends on 1) The system of claim 1, wherein: the hardware register comprises a life cycle state field and an initialization phase field. ### Claim 6 (depends on 1) The system of claim 1, wherein: the memory comprises: a non-volatile portion configured to store the application image; and a volatile portion addressable at the second address range and configured to store the system state verification parameter. ### Claim 7 (depends on 6) The system of claim 6, wherein: the system state verification parameter has a value that depends on a value of the system state data. ### Claim 8 A method, comprising: executing an application image to initialize a computing system; storing system state data associated with the initializing of the computing system and having a first Hamming distance in a hardware register having at least a first lockable until reset bit and being addressable at a first address range; storing a system state verification parameter in a system memory addressable at a second address range different than the first address range; combining the system state data and the system state verification parameter to generate a combined system state verification parameter having a second Hamming distance greater than the first Hamming distance; and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value. ### Claim 9 (depends on 8) The method of claim 8, wherein: the hardware register comprises a lock until reset register comprising the first lockable until reset bit; and the method comprises locking the hardware register during the initializing of the system. ### Claim 10 (depends on 8) The method of claim 8, wherein: storing the system state data in the hardware register comprises storing life cycle state data in the hardware register. ### Claim 11 (depends on 8) The method of claim 8, wherein: storing the system state data in the hardware register comprises storing the system state data in a sticky until reset register comprising the first lockable until reset bit. ### Claim 12 (depends on 11) The method of claim 11, comprising: setting the first lockable until reset bit a first bit of the hardware register after completion of a first phase of the initializing; and setting a second lockable until reset bit of the hardware register adjacent the first lockable until reset bit after completion of a second phase of the initializing. ### Claim 13 (depends on 11) The method of claim 11, comprising: setting the first lockable until reset bit of the hardware register responsive to a life cycle state of the system having a first value; and setting a second lockable until reset bit of the hardware register responsive to the life cycle state having a second value, wherein: identifying the fault condition comprises identifying the fault condition responsive to more than one bit being set in the hardware register after completion of the initializing of the system. ### Claim 14 (depends on 8) The method of claim 8, wherein: storing the system state data in the hardware register comprises storing a life cycle state field and an initialization phase field. ### Claim 15 (depends on 8) The method of claim 8, comprising: generating the system state verification parameter depending on a value of the system state data. ### Claim 16 (depends on 8) The method of claim 8, wherein: the hardware register comprises a sticky until reset register comprising the first lockable until reset bit and a second lockable until reset bit; and the method comprises: locking the first lockable until reset bit responsive to the first lockable until reset bit being set; and locking the second lockable until reset bit responsive to the second lockable until reset bit being set independent of the locking of the first lockable until reset bit. ### Claim 17 A non-transitory computer-readable medium storing instructions that when executed facilitate performance of operations comprising: initializing a computing system comprising a processor; storing system state data associated with the initializing of the computing system and having a first Hamming distance in a hardware register comprising at least a first lockable until reset bit and being addressable at a first address range; storing a system state verification parameter in a memory addressable at a second address range different than the first address range; combining the system state data in the hardware register and the system state verification parameter to generate a combined system state verification parameter having a second Hamming distance greater than the first Hamming distance; and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value after completion of the initialization of the computing system. ### Claim 18 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the operations comprise: setting the first lockable until reset bit of the hardware register after completion of a first phase of the initializing; and setting a second lockable until reset bit of the hardware register after completion of a second phase of the initializing. ### Claim 19 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the operations comprise: setting the first lockable until reset bit of the hardware register responsive to a life cycle state of the system having a first value; and setting a second lockable until reset bit of the hardware register responsive to the life cycle state having a second value, wherein: identifying the fault condition comprises identifying the fault condition responsive to more than one bit being set in the hardware register after completion of the initializing of the system. ### Claim 20 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the operations comprise: storing the system state verification parameter in a volatile portion of a system memory.