# US 12,762,079 B2 · System for implementing operations having dynamically-sized data structures on a reconfigurable processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,762,079 B2 - Document ID: US12762079B2 - Status: Granted - Kind: B2 - Application number: 18/884,690 - Filed: 2024-09-13 - Published: 2025-01-02 - Granted: 2026-10-13 - Earliest claimed: 2022-02-14 - Assignees: SambaNova Systems, Inc. - Applicants: SambaNova Systems, Inc. - Inventors: Abhishek Srivastava; Matthew Vilim; Raghu Prabhakar; Sankar Rachuru; Zhekun Zhang; Matheen Musaddiq; Apurv Vivek; Sitanshu Gupta; Ayesha Siddiqua - Web page: https://patentgrep.com/patent/US12762079B2 ## CPC - G06F 13/4059: {where the synchronisation uses buffers, e.g. for speed matching between buses} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data processing system for implementing operations that generate a dynamically-sized output includes a reconfigurable processor that is configured to implement first and second operations and control circuitry. The first operation generates an output, whose size is unknown during a configuration phase. The second operation receives the output as an input. During a write operation, the first operation is enabled to write a first portion of the output to a first portion of a buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer. The control circuity includes a control unit that: directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation. ## Claims ### Claim 1 A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor configured to: implement a first operation that generates an output, wherein a size of the output is unknown during a configuration phase; implement a second operation that receives the output of the first operation as an input; and wherein, during a write operation, the first operation is enabled to write a first portion of the output to a first portion of a buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer; and control circuitry, comprising: a control unit circuitry that: directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation. ### Claim 2 (depends on 1) The data processing system of claim 1, wherein the reconfigurable processor comprises arrays of coarse-grained reconfigurable (CGR) units that implement the first and second operations. ### Claim 3 (depends on 1) The data processing system of claim 1, wherein the control circuitry further comprises: a recording unit circuitry that generates control data that is indicative of the size of the output. ### Claim 4 (depends on 3) The data processing system of claim 3, wherein the recording unit generates the control data while the first operation generates the output. ### Claim 5 (depends on 4) The data processing system of claim 4, wherein the recording unit comprises: a counter that counts a number of elements in the output to generate the control data. ### Claim 6 (depends on 5) The data processing system of claim 5, wherein the counter increments conditionally based on a predicate of the first operation. ### Claim 7 (depends on 3) The data processing system of claim 3, wherein the control unit fetches the control data from the recording unit. ### Claim 8 (depends on 7) The data processing system of claim 7, wherein the control unit provides the control data to the second operation, wherein the second operation processes the input based on the control data. ### Claim 9 (depends on 7) The data processing system of claim 7, further comprising: external memory that is coupled to the reconfigurable processor, wherein the control unit stores the control data in the external memory, and wherein the second operation retrieves the control data from the external memory. ### Claim 10 (depends on 1) The data processing system of claim 1, wherein the control circuitry further comprises: a synchronization unit circuitry that sends a signal to the second operation when the first operation has generated the output. ### Claim 11 (depends on 10) The data processing system of claim 10, wherein the reconfigurable processor is configured to enable the first operation to write, when the first operation has finished writing the first portion of the output and the second operation has finished reading the first portion of the input, a second portion of the output to the second portion of the buffer, while the second operation reads the first portion of the output from the first portion of the buffer as a second portion of the input. ### Claim 12 (depends on 1) The data processing system of claim 1, further comprising: a compiler that generates configuration data for configuring the reconfigurable processor to implement the first operation, the second operation, and the control circuitry. ### Claim 13 (depends on 12) The data processing system of claim 12, wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, and wherein the compiler generates in the configuration data a first connection for the output and a second connection for the input, wherein each one of the first and second connections is suitable for a transmission of the predetermined maximum number of elements. ### Claim 14 (depends on 1) The data processing system of claim 1, further comprising: runtime logic that is configured to program the reconfigurable processor with configuration data such that the reconfigurable processor implements the first operation, the second operation, and the control circuitry. ### Claim 15 A method of operating a data processing system that comprises a reconfigurable processor, comprising: configuring the reconfigurable processor such that the reconfigurable processor implements: a first operation that generates an output, wherein a size of the output is unknown during a configuration phase, a second operation that receives the output of the first operation as an input, a write operation that stores the output in a buffer, wherein the first operation is enabled to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer, and control circuitry that comprises: a control unit circuitry that directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation. ### Claim 16 (depends on 15) The method of claim 15, further comprising: configuring the reconfigurable processor such that the control circuitry further comprises: a recording unit circuitry that generates control data that is indicative of the size of the output, wherein the control unit circuitry provides the control data to the second operation, and wherein the second operation processes the input based on the control data; and a synchronization unit circuitry that sends a signal to the second operation when the first operation has generated the output. ### Claim 17 (depends on 15) The method of claim 15, wherein the data processing system further comprises a compiler, further comprising: generating, with the compiler, configuration data for configuring the reconfigurable processor to implement the first operation, the second operation, and the control circuitry. ### Claim 18 (depends on 17) The method of claim 17, wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, the method further comprising: generating, with the compiler, in the configuration data a first connection for the output and a second connection for the input, wherein each one of the first and second connections is able to transport the predetermined maximum number of elements. ### Claim 19 (depends on 17) The method of claim 17, wherein the data processing system further comprises runtime logic, and wherein configuring the reconfigurable processor further comprises: programming, with the runtime logic, the reconfigurable processor with the configuration data. ### Claim 20 A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a data processing system that comprises a reconfigurable processor, the instructions comprising: configuring the reconfigurable processor with configuration data such that the reconfigurable processor implements: a first operation that generates an output, wherein a size of the output is unknown, a second operation that receives the output of the first operation as an input, a write operation that stores the output in a buffer, wherein the first operation is enabled to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer, and control circuitry that comprises a control unit circuitry that directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.