US 12,762,078 B2Granted

Memory controller communicating with vertically stacked dies and semiconductor device including the same

AssigneeSamsung Electronics Co., Ltd.

InventorsJihun Oh, Geonho Kim, Ilho Jung, Kyeongkeun Kang, Dongha Kim, Changyoung Bae, Kwanyeob Chae

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Abstract

A semiconductor device includes at least one core die and a logic die communicating with the core die via a plurality of through-silicon vias. The logic die includes a memory controller configured to control a memory operation of the core die and a PHY region configured to receive first input signals based on a first protocol from the memory controller and transmit first output signals generated based on the first input signals to the core die via the plurality of TSVs. The PHY region includes a protocol converter configured to perform alignment processing on bits of the first input signals so as to convert the protocol of the first input signals into a second protocol and then output the first input signals based on the second protocol, wherein the second protocol supports multi-phase communication between the PHY region and the core die.

Claims20

Dependent claims

A semiconductor device comprising:

at least one core die comprising a memory cell array;
and
a logic die communicating with the at least one core die via a plurality of through-silicon vias (TSVs),
wherein the logic die comprises:
a memory controller configured to control a memory operation of the at least one core die;
and
a physical (PHY) region configured to receive first input signals based on a first protocol from the memory controller, generate first output signals of a second protocol based on the first input signals, and transmit the first output signals to the at least one core die via the plurality of TSVs,
wherein the PHY region comprises:
a protocol converter configured to perform alignment processing on first bits of the first input signals so as to convert the first input signals from the first protocol into the first output signals of the second protocol;
and
a plurality of signal processing blocks configured to process the first output signals in parallel and in synchronization with respective phases of a plurality of internal clocks having multi-phases, and
wherein the second protocol is based on a multi-phase communication between the PHY region and the at least one core die.

9 more elements

A semiconductor device comprising:

at least one first die comprising a memory cell array;
and
a second die comprising:
a memory controller configured to control a memory operation of the at least one first die, and
a physical (PHY) region configured to communicate, based on a first protocol, with the memory controller and communicate, based on a second protocol, with the at least one first die via a plurality of through-silicon vias (TSVs),
wherein the PHY region comprises:
a protocol converter configured to perform protocol conversion based on an alignment processing for rearranging first bits of a command/address provided from the memory controller;
and
first to N-th signal processing blocks configured to:
process the rearranged bits of the command/address output from the protocol converter in synchronization with first to N-th internal clocks having multi-phases, and
output the rearranged bits of the command/address having multi-phases,
where N is an integer of two or more.

9 more elements

A memory controller comprising:

a memory control unit configured to control a memory operation of a memory device;
and
a physical (PHY) region configured to:
receive first input signals based on a first protocol from the memory control unit, and
transmit first output signals generated based on the first input signals to the memory device via a plurality of through-silicon vias (TSVs),
wherein the PHY region comprises:
a protocol converter configured to:
convert, based on alignment processing for rearranging bits of the first input signals, a protocol of the first input signals into a second protocol, and
output the first input signals having the second protocol, wherein the second protocol is based on multi-phase communication between the PHY region and the memory device;
and
first to N-th signal processing blocks configured to:
process the bits of the first input signals output from the protocol converter in synchronization with first to N-th internal clocks having multi-phases, and
generate the first output signals having multi-phases, wherein N is an integer of two or more.

10 more elements

Dependencies are inferred from the claim text.