# US 12,762,076 B2 · Interface method for transmitting and receiving data between functional blocks in system on chip, and system on chip using same

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- Number: US 12,762,076 B2
- Document ID: US12762076B2
- Status: Granted
- Kind: B2
- Application number: 18/369,345
- Filed: 2023-09-18
- Published: 2024-01-04
- Granted: 2026-10-13
- Earliest claimed: 2021-07-27
- Assignees: Semifive Inc.
- Applicants: Semifive Inc.
- Inventors: Sung Su Kim
- Web page: https://patentgrep.com/patent/US12762076B2

## CPC

- G06F 13/38: Information transfer, e.g. on bus (G06F13/14 takes precedence)
- G06F 2213/40: Bus coupling
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An interface method in a system-on-chip includes: a process of transmitting, by a first circuit unit, first payload data transferred from a first functional block and a first signal for requesting buffer allocation for storing the first payload data to a second circuit unit, and decreasing a resource value in which an initial value is set to correspond to the number of payload data which may be stored in a buffer provided in the second circuit unit by one; a process of storing, by the second circuit unit, the first payload data in the buffer according to the first signal; a process of withdrawing, by the second circuit unit, payload data selected among the payload data stored in the buffer, and transferring the payload data to a second functional block, and transmitting a second signal indicating that the buffer is empty to the first circuit unit; and a process of increasing, by the first circuit unit, the resource value by one.

## Claims

### Claim 1

An interface method in a system-on-chip, comprising:
setting, by a first circuit unit, a first resource value to a first initial value corresponding to a number of payload data capable of being stored in a first buffer provided in a second circuit unit;
transmitting, by the first circuit unit, first payload data transferred from a first functional block and a first signal for requesting buffer allocation for storing the first payload data to the second circuit unit, and decreasing the first resource value by one;
storing, by the second circuit unit, the first payload data in the first buffer according to the first signal;
withdrawing, by the second circuit unit, payload data selected among the payload data stored in the first buffer, and transferring the payload data to a second functional block, and transmitting a second signal indicating that the first buffer is empty to the first circuit unit;
increasing, by the first circuit unit, the first resource value by one according to the second signal;
setting, by the second circuit unit, a second resource value to a second initial value corresponding to a number of payload data capable of being stored in a second buffer provided in the first circuit unit;
transmitting, by the second circuit unit, second payload data transferred from a third functional block and a third signal for requesting buffer allocation for storing the second payload data to the first circuit unit, and decreasing the second resource value by one;
storing, by the first circuit unit, the second payload data in the second buffer according to the third signal;
withdrawing, by the first circuit unit, payload data selected among the payload data stored in the second buffer, and transferring the payload data to a fourth functional block, and transmitting a fourth signal indicating that the second buffer is empty to the second circuit unit; and
increasing, by the second circuit unit, the second resource value by one according to the fourth signal,
wherein a first clock signal used by the first circuit unit and a second clock signal used by the second circuit unit have different clock frequencies.

### Claim 2 (depends on 1)

The method of claim 1, wherein the fourth signal is transmitted through a channel through which the first payload data and the first signal are transmitted, and the second signal is transmitted through a channel through which the second payload data and the third signal are transmitted.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first payload data includes an ID capable of identifying a block which generates the first payload data, and the selected payload data among the payload data stored in the first buffer is selected according to a predetermined ID priority.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first circuit unit includes a first proxy circuit unit and the second circuit unit includes a second proxy circuit unit, the first proxy circuit unit and the second proxy circuit unit configured to assert a fifth signal and a sixth signal, respectively, based on the first resource value and the second resource value.

### Claim 5 (depends on 4)

The method of claim 4, wherein the fifth signal indicates that payload data is enabled to be accepted from the first functional block to the third circuit unit only when the first resource value has a non-zero value, and
wherein the sixth signal indicates that payload data is enabled to be accepted from the third functional block to the fourth circuit unit only when the second resource value has a non-zero value.

### Claim 6 (depends on 4)

The method of claim 4, wherein the first proxy circuit unit independently determines assertion of the fifth signal by locally maintaining the first resource value, and an output of the first proxy circuit unit triggers a transition of the fifth signal prior to a completion of synchronization of the second signal, and
wherein the second proxy circuit unit independently determines assertion of the sixth signal by locally maintaining the second resource value, such that an output of the second proxy circuit unit triggers a transition of the sixth signal prior to a completion of synchronization of the fourth signal.

### Claim 7

An interface method in a system-on-chip, comprising:
setting, by a first circuit unit, a resource value to an initial value corresponding to a number of payload data storable in a buffer of a second circuit unit;
transmitting, by the first circuit unit, first payload data transferred from a first functional block and a first signal for requesting buffer allocation for storing the first payload data to the second circuit unit, and decreasing the resource value by one;
storing, by the second circuit unit, the first payload data in the buffer according to the first signal;
withdrawing, by the second circuit unit, payload data selected among the payload data stored in the buffer and transferring the payload data to a second functional block, and transmitting a second signal indicating that the buffer is empty to the first circuit unit; and
increasing, by the first circuit unit, the resource value by one according to the second signal,
wherein a first clock signal used by the first circuit unit and a second clock signal used by the second circuit unit have different clock frequencies, and
wherein the first circuit unit includes a proxy circuit unit configured to assert a third signal for the first functional block based on the resource value.

### Claim 8 (depends on 7)

The method of claim 7, wherein the third signal indicates that payload data is enabled to be accepted from the first functional block to the first circuit unit only when the resource value has a non-zero value.

### Claim 9 (depends on 7)

The method of claim 7, wherein the proxy circuit unit independently determines assertion of the third signal to the first functional block by locally maintaining the resource value, and
wherein an output value of the proxy circuit unit triggers a transition of the third signal prior to a completion of synchronization of the second signal to the first clock signal.

### Claim 10 (depends on 7)

The method of claim 7, wherein the first circuit unit comprises an asynchronous proxy FIFO for managing the resource value,
wherein the asynchronous proxy FIFO is set to a size corresponding to the number of payload data which may be stored in the buffer of the second circuit unit, and
wherein the first circuit unit is configured to update the resource value by performing a push operation on the asynchronous proxy FIFO in response to the first signal and performing a pop operation on the asynchronous proxy FIFO in response to the second signal.

### Claim 11

A system-on-chip comprising:
a first circuit unit transmitting first payload data transferred from a first functional block and a first signal for requesting buffer allocation for storing the first payload data; and
a second circuit unit with a buffer, the second circuit unit storing the first payload data in the buffer according to the first signal, withdrawing payload data selected among the payload data stored in the buffer to transfer the selected payload data to a second functional block, and transmitting a second signal indicating that the buffer is empty to the first circuit unit,
wherein the first circuit unit sets a resource value to an initial value corresponding to a number of payload data capable of being stored in the buffer, decreases the resource value by one when the first circuit unit transmitting the first payload data, and increases the resource value by one according to the second signal,
wherein a first clock signal used by the first circuit unit and a second clock signal used by the second circuit unit have different clock frequencies, and
wherein the first circuit unit includes a proxy circuit unit configured to assert a third signal for the first functional block based on the resource value.

### Claim 12 (depends on 11)

The system-on-chip of claim 11, wherein the third signal indicates that payload data is enabled to be accepted from the first functional block to the first circuit unit only when the resource value has a non-zero value.

### Claim 13 (depends on 11)

The system-on-chip of claim 11, wherein the proxy circuit unit independently determines assertion of the third signal by locally maintaining the resource value, and
wherein an output value of the proxy circuit unit triggers a transition of the third signal prior to a completion of synchronization of the second signal to the first clock signal.