Runtime memory system with unpredictably assigned multiplexed memory bus lines

Abstract

This document describes technology for a runtime memory system that utilizes unpredictable multiplexing of memory bus lines. The technology dynamically reassigns data and/or address bus connections between a processor and its runtime memory during warm reset operations. The bus line assignments are made through a multiplexing mechanism—for example, data bus line 01 from the processor may be reassigned to link with bus line 23 at the runtime memory system interface. When a warm reset occurs, the physical mapping of memory locations changes due to this bus line reassignment. The system maintains standard memory operations while implementing this dynamic bus line configuration. Malicious software relying upon memory-resident exploit becomes inoperable after warm reset due to the changed physical memory topology created by the bus line reassignment process.

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