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US 12,762,069 B2Granted
Training and operations with a double buffered memory topology
AssigneeRambus Inc.
InventorsChi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
Life of this patent
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Abstract
System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).
Claims19
A system comprising:
- a dual in-line memory module (DIMM) comprising a plurality of memory devices;
- a driver circuit coupled to the DIMM, wherein the driver circuit is configured to receive a first write command from a memory controller, the first write command to instruct the DIMM to store data;
- and
- a data buffer coupled to the DIMM, wherein the data buffer is configured to receive a second write command from the memory controller, the second write command to cause the data buffer to send the data to the DIMM, wherein the second write command at least partially overlaps in time with the first write command.
1 more element
A method comprising:
- receiving, at a driver circuit coupled to a dual in-line memory module (DIMM) comprising a plurality of memory devices, a first write command from a memory controller, the first write command to instruct the DIMM to store data;
- and
- receiving, at a data buffer coupled to the DIMM, a second write command from the memory controller, the second write command to cause the data buffer to send the data to the DIMM, wherein the second write command at least partially overlaps in time with the first write command.
A system comprising:
- a dual in-line memory module (DIMM) comprising a plurality of memory devices;
- a driver circuit coupled to the DIMM, wherein the driver circuit is configured to receive, with a first time delay, a first write command from a memory controller, the first write command to instruct the DIMM to store data;
- and
- a data buffer coupled to the DIMM, wherein the data buffer is configured to receive, with a second time delay, a second write command from the memory controller, the second write command to cause the data buffer to send the data to the DIMM, wherein the first time delay of the first write command and the second time delay of the second write command are configured to allow for operation of the DIMM.
1 more element
Dependencies are inferred from the claim text.