# US 12,762,065 B2 · Memory device having a write-back cache storing cache data and scrub data

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- Number: US 12,762,065 B2
- Document ID: US12762065B2
- Status: Granted
- Kind: B2
- Application number: 17/972,493
- Filed: 2022-10-24
- Published: 2024-04-25
- Granted: 2026-10-13
- Earliest claimed: 2022-10-24
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Christophe Vincent Antoine Laurent; Ferdinando Bedeschi
- Web page: https://patentgrep.com/patent/US12762065B2

## CPC

- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 2212/305: being part of a memory device, e.g. cache DRAM
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems, methods, and apparatus for a memory device that stores a scrub list in a cache used to reduce data traffic to and from a memory array. In one approach, the cache merges the scrub list with cache data. Data in the scrub list can be identified and distinguished from the cache data by adding a one-bit scrub flag to each data entry in the merged cache. In this merged approach, the cache data shares the same memory as the scrub list. Read data that has an error is saved temporarily in this merged cache until the correct value for the data is written back into the memory array.

## Claims

### Claim 1

An apparatus comprising:
a cache; and
a memory controller configured to:
in response to receiving a first read command requesting a second data set, determine that the second data set is not stored in the cache, and read the second data set from a memory array;
in response to determining that the second data set read from the memory array has an error, correct the second data set, store the corrected second data set in the cache, and set a flag for the second data set; and
in response to receiving a second read command requesting the second data set, determine that the second data set is stored in the cache, determine the flag is set, write the corrected second data set from the cache to the memory array, and read the corrected second data set from the cache.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to:
receive the second read command from a host device; and
send the second data set to the host device.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the second data set is sent to the host device within a time window starting from receiving the second read command, and the second data set is written to the memory array within the time window.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to:
receive a third read command from a host device to read a third data set;
in response to receiving the third read command, determine whether the third data set is stored in the cache;
in response to determining that the third data set is not stored in the cache, read the third data set from a memory array;
determine whether the read third data set has an error;
in response to determining that the read third data set does not have an error, write the third data set in the cache with an indication that the third data set does not need correction; and
send the third data set to the host device.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to:
determine whether the cache is full; and
in response to determining that the cache is full, evict at least one data entry from the cache.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the second data set is stored at an address in the memory array, and the controller is further configured to determine whether the second data set is stored in the cache by determining whether the address is stored in the cache.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to:
receive a write command from a host device to write a new data set;
write the new data set at an address in the memory array;
determine whether the address is in the cache;
in response to determining that the address is in the cache, evict an old data set from the cache that corresponds to the address; and
write the new data set in the cache with an indication that the new data set does not need correction.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the controller is further configured to determine whether a scrub flag associated with the address is set.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to:
receive a write command from a host device to write a new data set at an address;
in response to receiving the write command, determine that the address is not in the cache; and
write the new data set in the cache with an indication that the new data set does not need correction.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to:
receive a write command from a host device to write a new data set at an address; and
in response to receiving the write command, write the new data set in the cache with an indication that the new data set does not need correction.

### Claim 11

An apparatus comprising:
a cache; and
a controller configured to:
determine that a first data set read from a memory array has an error, correct the first data set, store the corrected first data set in the cache, and set a scrub flag for the first data set;
receive a read command from a host device, the read command requesting the first data set;
in response to receiving the read command, determine the first data set is stored in the cache and that the scrub flag for the first data set is set;
in response to determining that the scrub flag is set, write back the corrected first data set from the cache to the memory array;
read the corrected first data set from the cache; and
send the corrected first data set to the host device.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the cache is further configured to store respective data for each address stored in the cache.

### Claim 13 (depends on 12)

The apparatus of claim 12, further comprising an error correction code engine, wherein the respective data stored for each address having a flag set has been corrected using the error correction code engine.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein the cache is further configured so that eviction of each address having a flag set requires that corrected data is written in a memory array at the respective address.

### Claim 15

A method comprising:
in response to determining that a first data set read from a memory array has an error, correcting the first data set;
storing the corrected first data set in a scrub area of a cache memory;
receiving a request to read the first data set;
in response to determining that the first data set is stored in the scrub area, writing back the corrected first data set from the scrub area to the memory array; and
providing the corrected first data set from the scrub area in reply to the request.

### Claim 16 (depends on 15)

The method of claim 15, wherein the request is a first request, the method further comprising:
receiving a second request to read a second data set;
in response to receiving the second request, determining whether the second data set is stored in the scrub area or a cache area;
in response to determining that the second data set is stored in one of the scrub area or the cache area, reading the second data set from the one of the scrub area or the cache area; and
providing the read second data set in reply to the second request.

### Claim 17 (depends on 15)

The method of claim 15, wherein the request is a first request, the method further comprising:
receiving a second request to read a second data set;
determining that the second data set has an error;
in response to determining that the second data set has an error, correcting the second data set and writing the corrected second data set in the scrub area; and
providing the corrected second data set in reply to the second request.

### Claim 18 (depends on 15)

The method of claim 15, wherein the request is a first request, the method further comprising:
receiving a second request to read a second data set;
reading the second data set;
determining that the second data set does not have an error;
in response to determining that the second data set does not have an error, writing the second data set in a cache area of the cache memory; and
providing the read second data set in reply to the second request.