Non-cacheable access handling in processor with virtually-tagged virtually-indexed data cache

A method for use in a microprocessor comprising a first-level data cache configured to operate with virtual addresses, comprising:

• performing a first lookup in the data cache of a virtual address specified by a load/store instruction;
• determining whether the virtual address misses in the data cache;
• in response to the virtual address missing in the data cache, generating a fill request that causes the processor to translate the virtual address into a physical address;
• receiving a response to the fill request that indicates the physical address is in a non-cacheable memory region and that is without data from the physical address;
• allocating a data-less entry in the data cache that includes an indication that the data-less entry is associated with a non-cacheable memory region;
• performing a second lookup of the virtual address in the data cache and determining that the virtual address hits in the data cache on the data-less entry;
• and
• determining from the hit data-less entry that the data-less entry is associated with a non-cacheable memory region accessible via a processor bus of the microprocessor.

A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor comprising:

• a first-level data cache configured to operate with virtual addresses;
• and
• a load/store circuit configured to:
• perform a first lookup in the data cache of a virtual address specified by a load/store instruction, determine that the virtual address misses in the data cache and, in response to the miss, generate a fill request that causes the microprocessor to translate the virtual address into a physical address;
• receive a response to the fill request that indicates the physical address is in a non-cacheable memory region and that is without data from the physical address;
• allocate a data-less entry in the data cache that includes an indication that the data-less entry is associated with a non-cacheable memory region;
• perform a second lookup of the virtual address in the data cache and determine that the virtual address hits in the data cache on the data-less entry;
• and
• determine from the hit data-less entry that the data-less entry is associated with a non-cacheable memory region accessible via a processor bus of the microprocessor.