US 12,762,058 B2 · Aliased mode for cache controller

Abstract

An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.

Claims20

Dependent claims

An apparatus comprising:

a memory including a first portion and a second portion;
at least one register configured to:
indicate whether the memory operates in an aliased mode or an un-aliased mode;
and
indicate ownership of the first portion to either a first processor core or a second processor core, and ownership of the second portion to the other of the first processor core and the second processor core;
and
a controller coupled to the memory and the at least one register, wherein the controller is configured to:
receive a first memory access instruction directed to a virtual address from the first processor core;
receive a second memory access instruction directed to the virtual address from the second processor core;
and
direct the first memory access instruction and the second memory access instruction to the memory based on the indication of the at least one register.

8 more elements

A method comprising:

receiving, by a controller of a memory, a first memory access instruction directed to a virtual address from a first processor core, wherein the memory includes a first portion and a second portion;
receiving, by the controller, a second memory access instruction directed to the virtual address from a second processor core;
and
directing, by the controller based on at least one register, the first memory access instruction and the second memory access instruction to the memory, wherein the at least one register indicates whether the memory operates in an aliased mode or an un-aliased mode and ownership of the first portion to either the first processor core or the second processor core, and ownership of the second portion to the other of the first processor core and the second processor core.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

18/797,945Filed 8 Aug 2024 · continuation

Priority

24 May 2019

Published

US 2025/0021481 A116 Jan 2025

Granted

13 Oct 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 12/0811
Multiuser, multiprocessor or multiprocessing cache systems: with multilevel cache hierarchies
G06F 12/10
In hierarchically structured memory systems, e.g. virtual memory systems: address translation
G06F 2212/608
Details of cache memory: details relating to cache mapping
G06F
Computing and data processing

Family

Application62/852,461Us provisional application · filed 24 May 2019

Application16/882,344Parent of this continuation · filed 22 May 2020

Application17/847,131Parent of this continuation · filed 22 Jun 2022

US 11,392,498 B2Parent of this continuation · filed 19 Jul 2022

US 2025/0021481 A1Pre-grant publication · published 16 Jan 2025

US 12,086,064 B2Parent of this continuation

US 2021/0365374 A1Published application

US 2022/0327055 A1Published application

US 12,762,058 B2This patent

From the US filing history. Foreign family members aren’t listed.

Aliased mode for cache controller

Life of this patent

Aliased mode for cache controller

Life of this patent

Abstract

Claims20