# US 12,762,052 B2 · Logical-to-physical mapping for zoned namespace memory systems with a data cache

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- Number: US 12,762,052 B2
- Document ID: US12762052B2
- Status: Granted
- Kind: B2
- Application number: 19/209,259
- Filed: 2025-05-15
- Published: 2025-11-27
- Granted: 2026-10-13
- Earliest claimed: 2024-05-23
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: John J. Kane; Paul Roger Stonelake
- Web page: https://patentgrep.com/patent/US12762052B2

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 12/0871: Allocation or management of cache space
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods, systems, and devices for logical-to-physical (L2P) mapping for zoned namespace (ZNS) memory systems are described. A memory system may include a cache, such as a single-level cell (SLC) cache in front of a quad-level cell (QLC) non-volatile memory device. The cache may include a multiple layer L2P table to map logical block addresses (LBAs) of data to physical addresses of the cache. In some examples, the L2P table may be sparsely populated to hold a quantity of LBAs corresponding to a quantity of open zones, and may be organized into groups of L2P entries to address a full logical space of the memory device. L2 Region boundaries may be aligned on zone boundaries by utilizing an integer quantity of L2 regions for each zone, an integer quantity of L2P entries per L2 region, or both, to reduce complexity and write amplification while improving performance.

## Claims

### Claim 1

A memory system, comprising:
one or more caches comprising a plurality of memory cells of a first type;
one or more memory arrays coupled with the one or more caches and comprising a plurality of memory cells of a second type, wherein the plurality of memory cells are included in a plurality of zones, each zone comprising one or more blocks of memory cells; and
processing circuitry configured to:
receive a write command comprising data and a set of logical block addresses associated with the data, the data for storage in the one or more memory arrays, wherein the set of logical block addresses is associated with one or more zones of the plurality of zones of the one or more memory arrays;
store, to a cache of the one or more caches based at least in part on the write command, one or more entries that map the set of logical block addresses to respective physical addresses of a plurality of physical addresses in the cache, wherein each entry of the one or more entries comprises mapping information for a respective zone of the one or more zones;
write the data to the respective physical addresses in the cache based at least in part on storing the one or more entries in the cache; and
copy the data from the cache to the one or more zones in the one or more memory arrays based at least in part on writing the data to the respective physical addresses in the cache.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein, to store the one or more entries to the cache, the processing circuitry is configured to:
store the one or more entries to a logical-to-physical (L2P) table that maps a plurality of logical block addresses comprising the set of logical block addresses to the plurality of physical addresses in the cache of the one or more caches.

### Claim 3 (depends on 2)

The memory system of claim 2, wherein:
the L2P table comprises a first table of one or more first entries and a second table of one or more second entries,
the second table comprises the one or more entries, and
each first entry of the first table corresponds to a respective second entry of the second table.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein the processing circuitry is further configured to:
allocate, based at least in part on the write command comprising the data and the set of logical block addresses associated with the data, one or more portions of the cache of the one or more caches for storing one or more groups of entries, each group of entries associated with a respective zone of the one or more zones, wherein storing the one or more entries to the cache is based at least in part on the allocating.

### Claim 5 (depends on 4)

The memory system of claim 4, wherein the processing circuitry is further configured to:
deallocate the one or more portions of the cache for storing the one or more groups of entries based at least in part on copying the data from the cache to the one or more zones in the one or more memory arrays.

### Claim 6 (depends on 5)

The memory system of claim 5, wherein the processing circuitry is further configured to:
update a list of available portions of the cache based at least in part on the allocating, the deallocating, or both.

### Claim 7 (depends on 1)

The memory system of claim 1, wherein, to copy the data from the cache to the one or more zones in the one or more memory arrays, the processing circuitry is configured to:
copy the data based at least in part on the data being mapped to one or more groups of entries each comprising at least a threshold quantity of entries, wherein a first subset of the data associated with a first group of entries is copied to a first zone of the one or more zones based at least in part on the first group of entries comprising first mapping information for the first zone.

### Claim 8 (depends on 1)

The memory system of claim 1, wherein the processing circuitry is further configured to:
copy the one or more entries from the cache to the one or more memory arrays based at least in part on a quantity of entries in the cache satisfying a threshold, based at least in part on a power off event associated with the memory system, or both.

### Claim 9 (depends on 1)

The memory system of claim 1, wherein a size of each zone of the one or more zones corresponds to an integer quantity of entries of the one or more entries.

### Claim 10 (depends on 1)

The memory system of claim 1, wherein:
the plurality of memory cells of the first type in the one or more caches comprise a plurality of single-level memory cells, and
the plurality of memory cells of the second type in the one or more memory arrays comprise a plurality of multi-level memory cells.

### Claim 11

A method, comprising:
receiving, by a memory system, a write command comprising data and a set of logical block addresses associated with the data, the data for storage in a memory array of the memory system, wherein the set of logical block addresses is associated with one or more zones of memory cells of a plurality of zones of memory cells in the memory array;
storing, to a cache of the memory system based at least in part on the write command, one or more entries that map the set of logical block addresses to respective physical addresses of a plurality of physical addresses in the cache, wherein each entry of the one or more entries comprises mapping information for a respective zone of the one or more zones of memory cells;
writing the data to the respective physical addresses in the cache based at least in part on storing the one or more entries in the cache; and
transferring the data from the cache to the one or more zones in the memory array based at least in part on writing the data to the respective physical addresses in the cache.

### Claim 12 (depends on 11)

The method of claim 11, wherein storing the one or more entries to the cache comprises:
storing the one or more entries to a logical-to-physical (L2P) table that maps a plurality of logical block addresses comprising the set of logical block addresses to the plurality of physical addresses in the cache of the memory system.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
the L2P table comprises a first table of one or more first entries and a second table of one or more second entries,
the second table comprises the one or more entries, and
each first entry of the first table corresponds to a respective second entry of the second table.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
allocating, based at least in part on the write command comprising the data and the set of logical block addresses associated with the data, one or more portions of the cache for storing one or more groups of entries, each group of entries associated with a respective zone of the one or more zones, wherein storing the one or more entries to the cache is based at least in part on the allocating.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
deallocating the one or more portions of the cache for storing the one or more groups of entries based at least in part on transferring the data from the cache to the one or more zones in the memory array.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
updating a list of available portions of the cache based at least in part on the allocating, the deallocating, or both.

### Claim 17 (depends on 11)

The method of claim 11, wherein transferring the data from the cache to the one or more zones in the memory array comprises:
transferring the data based at least in part on the data being mapped to one or more groups of entries each comprising at least a threshold quantity of entries, wherein a first subset of the data associated with a first group of entries is transferred to a first zone of the one or more zones based at least in part on the first group of entries comprising first mapping information for the first zone.

### Claim 18 (depends on 11)

The method of claim 11, further comprising:
copying the one or more entries from the cache to the memory array based at least in part on a quantity of entries in the cache satisfying a threshold, based at least in part on a power off event associated with the memory system, or both.

### Claim 19 (depends on 11)

The method of claim 11, wherein a size of each zone of the one or more zones corresponds to an integer quantity of entries of the one or more entries.

### Claim 20 (depends on 11)

The method of claim 11, wherein:
the cache comprises a plurality of single-level memory cells, and
the memory array comprises a plurality of multi-level memory cells.

### Claim 21

A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
receive, by a memory system, a write command comprising data and a set of logical block addresses associated with the data, the data for storage in a memory array of the memory system, wherein the set of logical block addresses is associated with one or more zones of memory cells of a plurality of zones of memory cells in the memory array;
store, to a cache of the memory system based at least in part on the write command, one or more entries that map the set of logical block addresses to respective physical addresses of a plurality of physical addresses in the cache, wherein each entry of the one or more entries comprises mapping information for a respective zone of the one or more zones of memory cells;
write the data to the respective physical addresses in the cache based at least in part on storing the one or more entries in the cache; and
transfer the data from the cache to the one or more zones in the memory array based at least in part on writing the data to the respective physical addresses in the cache.

### Claim 22 (depends on 21)

The non-transitory computer-readable medium of claim 21, wherein the instructions to store the one or more entries to the cache are executable by the one or more processors to:
store the one or more entries to a logical-to-physical (L2P) table that maps a plurality of logical block addresses comprising the set of logical block addresses to the plurality of physical addresses in the cache of the memory system.

### Claim 23 (depends on 22)

The non-transitory computer-readable medium of claim 22, wherein:
the L2P table comprises a first table of one or more first entries and a second table of one or more second entries,
the second table comprises the one or more entries, and
each first entry of the first table corresponds to a respective second entry of the second table.

### Claim 24

A memory system, comprising:
one or more caches comprising a plurality of single-level memory cells;
one or more memory arrays coupled with the one or more caches and comprising a plurality of multi-level memory cells, wherein the plurality of multi-level memory cells are included in a plurality of zones, each zone comprising one or more blocks of memory cells; and
processing circuitry configured to:
receive a write command comprising data and a set of logical block addresses associated with the data, the data for storage in the one or more memory arrays, wherein the set of logical block addresses is associated with one or more zones of the plurality of zones of the one or more memory arrays;
store, to a logical-to-physical (L2P) table in a cache of the one or more caches based at least in part on the write command, one or more L2P entries that map the set of logical block addresses to respective physical addresses of a plurality of physical addresses in the cache, wherein each L2P entry of the one or more L2P entries comprises mapping information for a respective zone of the one or more zones, and wherein a size of each zone of the one or more zones corresponds to an integer quantity of L2P entries of the one or more L2P entries;
write the data to the respective physical addresses in the cache based at least in part on storing the one or more L2P entries in the L2P table, wherein the cache is configured to store data for a subset of the plurality of zones that comprises the one or more zones;
copy the data from the cache to the one or more zones in the one or more memory arrays based at least in part on writing the data to the respective physical addresses in the cache; and
deallocate, based at least in part on copying the data from the cache to the one or more zones in the one or more memory arrays, one or more portions of the cache allocated for storing one or more groups of L2P entries.

### Claim 25 (depends on 24)

The memory system of claim 24, wherein:
the L2P table comprises a first table of one or more first entries and a second table of one or more second entries,
the second table comprises the one or more L2P entries, and
each first entry of the first table corresponds to a respective second entry of the second table.

### Claim 26 (depends on 24)

The memory system of claim 24, wherein the processing circuitry is further configured to:
allocate, based at least in part on the write command comprising the data and the set of logical block addresses associated with the data, the one or more portions of the cache for storing the one or more groups of L2P entries, each group of L2P entries associated with a respective zone of the one or more zones, wherein storing the one or more L2P entries to the L2P table in the cache is based at least in part on the allocating.

### Claim 27 (depends on 26)

The memory system of claim 26, wherein the processing circuitry is further configured to:
update a list of available portions of the cache based at least in part on the allocating, the deallocating, or both.

### Claim 28

A method, comprising:
receiving, by a memory system, a write command comprising data and a set of logical block addresses associated with the data, the data for storage in a memory array of the memory system, wherein the set of logical block addresses is associated with one or more zones of multi-level memory cells of a plurality of zones of multi-level memory cells in the memory array;
storing, to a logical-to-physical (L2P) table in one or more single-level memory cells of a cache of the memory system based at least in part on the write command, one or more L2P entries that map the set of logical block addresses to respective physical addresses of a plurality of physical addresses in the cache, wherein each L2P entry of the one or more L2P entries comprises mapping information for a respective zone of the one or more zones of multi-level memory cells, and wherein a size of each zone of the one or more zones corresponds to an integer quantity of L2P entries of the one or more L2P entries;
writing the data to the respective physical addresses in the cache based at least in part on storing the one or more L2P entries in the L2P table, wherein the cache is configured to store data for a subset of the plurality of zones that comprises the one or more zones;
transferring the data from the one or more single-level memory cells of the cache to the one or more zones of multi-level memory cells in the memory array based at least in part on writing the data to the respective physical addresses in the cache; and
deallocating, based at least in part on transferring the data from the cache to the one or more zones in the memory array, one or more portions of the cache allocated for storing one or more groups of L2P entries.

### Claim 29 (depends on 28)

The method of claim 28, wherein:
the L2P table comprises a first table of one or more first entries and a second table of one or more second entries,
the second table comprises the one or more L2P entries, and
each first entry of the first table corresponds to a respective second entry of the second table.

### Claim 30 (depends on 28)

The method of claim 28, further comprising:
allocating, based at least in part on the write command comprising the data and the set of logical block addresses associated with the data, the one or more portions of the cache for storing the one or more groups of L2P entries, each group of L2P entries associated with a respective zone of the one or more zones, wherein storing the one or more L2P entries to the L2P table in the one or more single-level memory cells of the cache is based at least in part on the allocating.