Error rate measurement apparatus and signal detection method

An error rate measurement apparatus for measuring an error rate of an input signal from a device under test (DUT), the error rate measurement apparatus comprising:

• a display;
• a field-programmable gate array (FPGA) configured to:
• generate an internal signal consisting of a specific pattern expected to be output from the DUT according to a state of a link state management mechanism;
• hold a part of a head of the internal signal as a reference signal;
• detect a head of the specific pattern in the input signal by comparing the reference signal with the input signal;
• output a detection signal synchronized with a timing at which the head of the specific pattern is detected;
• and
• hold the detection signal;
• and
• a controller that causes the display to display a detection notification image indicating that the head of the specific pattern is detected, during a period in which the detection signal is held.