ECS circuit and method, and memory

An error check and scrub (ECS) circuit, comprising an ECS control module, a command generation module, an address counting module, and an error tracking and recording module,

• the ECS control module being configured to:
• receive a mode control signal, and generate an ECS command signal based on the mode control signal;
• the command generation module being configured to generate an internal command signal based on the ECS command signal, the internal command signal being configured to perform a corresponding ECS operation;
• the address counting module being configured to:
• perform address counting based on the internal command signal, and generate a counting end signal when counting is completed for a target address;
• and
• the error tracking and recording module being configured to:
• receive an error signal, and generate an error tracking signal based on the counting end signal and the error signal, the error tracking signal being configured to record error information of the ECS operation;
• wherein the command generation module comprises an internal command generation module and a preset timing condition control module,
• the internal command generation module being configured to successively generate an active signal, a read command signal, a write command signal, and a precharge signal based on a preset timing condition after the ECS command signal is received;
• the preset timing condition control module being configured to:
• control a time interval between the active signal and the read command signal to meet a first timing condition, control a time interval between the read command signal and the write command signal to meet a second timing condition, and control a time interval between the write command signal and the precharge signal to meet a third timing condition;
• and
• the preset timing condition comprising the first timing condition, the second timing condition, and the third timing condition.