Host error control matrix
AssigneeMicron Technology, Inc.
InventorsScott E. Schaefer, Joseph G. Garofalo
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsScott E. Schaefer, Joseph G. Garofalo
Estimating the term…
Methods, systems, and devices for host error control matrix are described. A host device may implement a parity check matrix for generating error control information with a relatively low likelihood that a multi-bit error in a codeword associated with the error control information is mistaken for a single-bit error. The host device may implement a parity check matrix patterned such that when the error control information is generated, there is a relatively low likelihood that an error code resulting from a comparison of the error control information will yield an indication of a single-bit error when a multi-bit error occurs. For example, the host device may compare first error control information generated for a codeword and transmitted to a memory device with second error control information generated after receiving the codeword from the memory device, and generate an error code using the results of the comparison.
A method, comprising:
An automotive memory system, comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.