# US 12,762,012 B2 · Semiconductor memory apparatus configured to perform an error check > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,762,012 B2 - Document ID: US12762012B2 - Status: Granted - Kind: B2 - Application number: 18/733,308 - Filed: 2024-06-04 - Published: 2025-07-24 - Granted: 2026-10-13 - Earliest claimed: 2024-01-18 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Ji Soo Kim - Web page: https://patentgrep.com/patent/US12762012B2 ## CPC - G06F 11/102: {Error in check bits} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A semiconductor memory apparatus includes an encoding circuit, a read path circuit, a transmitter circuit, and a read error check circuit. The encoding circuit is configured to encode bank data to generate a read symbol. The read path circuit is configured to transmit the read symbol to the transmitter circuit. The transmitter circuit is configured to generate a multi-level signal based on the read symbol. The read error check circuit is configured to determine whether an error has occurred in the transmission of the read symbol from the encoding circuit to the transmitter circuit through the read path circuit. ## Claims ### Claim 1 A semiconductor memory apparatus comprising: an encoding circuit configured to encode bank data output from a memory cell array to generate a read symbol and configured to generate a first check bit from the read symbol; a read path circuit configured to transmit the read symbol; a transmitter circuit configured to generate a multi-level signal based on the read symbol received from the read path circuit, and configured to generate a second check bit from the read symbol; and a read error check circuit configured to generate a read error signal based on the first check bit and the second check bit. ### Claim 2 (depends on 1) The semiconductor memory apparatus of claim 1, wherein the encoding circuit includes an encoder that encodes an 11-bit data signal of the bank data into seven symbols. ### Claim 3 (depends on 1) The semiconductor memory apparatus of claim 1, wherein the read path circuit comprises: a latch circuit configured to latch the read symbol output from the encoding circuit; and a read global transmission line that transmits an output signal of the latch circuit, wherein the transmitter circuit is configured to receive the read symbol through the read global transmission line. ### Claim 4 (depends on 1) The semiconductor memory apparatus of claim 1, wherein the encoding circuit is configured to generate at least one bit among bits of the read symbol as the first check bit, and the transmitter circuit is configured to generate a bit for the same bit position as the at least one bit among bits of the read symbol as the second check bit. ### Claim 5 (depends on 1) The semiconductor memory apparatus of claim 1, wherein the encoding circuit is configured to perform a logic operation on a plurality of bits among bits of the read symbol to generate the first check bit, and the transmitter circuit is configured to perform a logic operation on a plurality of bits for the same bit position(s) as the plurality of bits among bits of the read symbol to generate the second check bit. ### Claim 6 (depends on 1) The semiconductor memory apparatus of claim 1, further comprising a delay circuit configured to delay the first check bit, wherein a delay time of the delay circuit corresponds to a time at which the read symbol is transmitted from the encoding circuit to the transmitter circuit. ### Claim 7 (depends on 1) The semiconductor memory apparatus of claim 1, wherein the read error check circuit is configured to generate the read error signal having a first voltage level when the first and second check bits have the same logic level, configured to generate the read error signal having a second voltage level when the first and second check bits have different logic levels and the first check bit has a first logic level, and configured to generate the read error signal having a third voltage level when the first and second check bits have different logic levels and the first check bit has a second logic level. ### Claim 8 (depends on 1) The semiconductor memory apparatus of claim 1, wherein the read error check circuit comprises: a decision circuit configured to output a first selection signal and a second selection signal having the same voltage level when the first and second check bits have the same logic level, and configured to output the first check bit as the first selection signal and to output the second check bit as the second selection signal, when the first and second check bits have different logic levels; a symbol generation circuit configured to generate a first transmission bit based on whether the first and second check bits have the same logic level and a logic level of the first selection signal, and configured to generate the second selection signal as a second transmission bit; and an output driver configured to generate the read error signal based on the first and second transmission bits. ### Claim 9 (depends on 8) The semiconductor memory apparatus of claim 8, wherein the symbol generation circuit is configured to output the first selection signal as the first transmission bit and to output the second selection signal as the second transmission bit, when the first and second check bits have the same logic level, configured to output the first selection signal as the first transmission bit when the first and second check bits have different logic levels and the first selection signal has a first logic level, and configured to generate the first transmission bit having a logic level opposite to the first selection signal when the first and second check bits have different logic levels and the first selection signal has a second logic level. ### Claim 10 A semiconductor memory apparatus comprising: a first memory bank that outputs a first bank data; a second memory bank that outputs a second bank data; a first encoding circuit configured to encode the first bank data to generate a first read symbol, and configured to generate a first check bit from the first read symbol; a second encoding circuit configured to encode the second bank data to generate a second read symbol, and configured to generate a second check bit from the second read symbol; a first read path circuit configured to transmit the first read symbol, and configured to output one of the first read symbol and the second read symbol as a first selected read symbol based on a channel selection signal; a second read path circuit configured to transmit the second read symbol, and configured to provide the second read symbol to the first read path circuit or output the second read symbol as a second selected read symbol based on a channel mode signal; a first transmitter circuit configured to generate a first multi-level signal based on the first selected read symbol, and configured to generate a third check bit from the first selected read symbol; a second transmitter circuit configured to generate a second multi-level signal based on the second selected read symbol, and configured to generate a fourth check bit from the second selected read symbol; a first read error check circuit configured to generate a first read error signal based on one of the first and second check bits and the third check bit based on the channel selection signal; and a second read error check circuit configured to generate a second read error signal based on the second and fourth check bits. ### Claim 11 (depends on 10) The semiconductor memory apparatus of claim 10, further comprising a repeater that transmits the second read symbol from the second read path circuit to the first read path circuit. ### Claim 12 (depends on 10) The semiconductor memory apparatus of claim 10, wherein the first encoding circuit is configured to generate at least one bit among bits of the first read symbol as the first check bit, and the first transmitter circuit is configured to generate a bit for the same bit position as the at least one bit among bits of the first read symbol as the third check bit. ### Claim 13 (depends on 10) The semiconductor memory apparatus of claim 10, wherein the first encoding circuit is configured to perform a logic operation on a plurality of bits among bits of the first read symbol to generate the first check bit, and the first transmitter circuit is configured to perform a logic operation on a plurality of bits for the same bit position(s) as the plurality of bits among bits of the first read symbol to generate the third check bit. ### Claim 14 (depends on 10) The semiconductor memory apparatus of claim 10, wherein the second encoding circuit is configured to generate at least one bit among bits of the second read symbol as the second check bit, and the second transmitter circuit is configured to generate a bit for the same bit position as the at least one bit among bits of the second read symbol as the fourth check bit. ### Claim 15 (depends on 10) The semiconductor memory apparatus of claim 10, wherein the second encoding circuit is configured to perform a logic operation on a plurality of bits among bits of the second read symbol to generate the second check bit, and the second transmitter circuit is configured to perform a logic operation on a plurality of bits for the same bit position(s) as the plurality of bits among bits of the second read symbol to generate the fourth check bit. ### Claim 16 (depends on 10) The semiconductor memory apparatus of claim 10, wherein the first read error check circuit is configured to generate the first read error signal having a first voltage level when one of the first and second check bits and the third check bit have the same logic level, configured to generate the first read error signal having a second voltage level when one of the first and second check bits and the third check bit have different logic levels and one of the first and second check bits has a first logic level, and configured to generate the first read error signal having a third voltage level when one of the first and second check bits and the third check bit have different logic levels and one of the first and second check bits has a second logic level. ### Claim 17 (depends on 10) The semiconductor memory apparatus of claim 10, wherein the second read error check circuit is configured to generate the second read error signal having a first voltage level when the second and fourth check bits have the same logic level, configured to generate the second read error signal having a second voltage level when the second and fourth check bits have different logic levels and the second check bit has a first logic level, and configured to generate the second read error signal having a third voltage level when the second and fourth check bits have different logic levels and the second check bit has a second logic level.