# US 12,762,011 B2 · Configurable cache for coherent system

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- Number: US 12,762,011 B2
- Document ID: US12762011B2
- Status: Granted
- Kind: B2
- Application number: 18/939,018
- Filed: 2024-11-06
- Published: 2025-02-20
- Granted: 2026-10-13
- Earliest claimed: 2018-10-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Kai Chirca; Matthew David Pierson
- Web page: https://patentgrep.com/patent/US12762011B2

## CPC

- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0607: {by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}
- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/064: {Management of blocks}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 9/30101: {Special purpose registers}
- G06F 9/30123: {according to context, e.g. thread buffers}
- G06F 9/3897: {with adaptable data path}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/5016: {the resource being the memory}
- G06F 12/0607: {Interleaved addressing}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/0828: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/084: with a shared cache
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0857: {by multiple requestors}
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/10: Address translation
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine}
- G06F 13/1642: {with request queuing}
- G06F 13/1663: {Access to shared memory}
- G06F 13/1668: {Details of memory controller}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- H03M 13/015: {Simulation or testing of codes, e.g. bit error rate [BER] measurements}
- H03M 13/098: {using single parity bit}
- H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance}
- H03M 13/276: {Interleaving address generation}
- H03M 13/2785: {Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location}
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible
- G06F 12/0851: {Cache with interleaved addressing}
- G06F 12/0862: with prefetch
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1016: Performance improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1048: Scalability
- G06F 2212/304: In main memory subsystem
- G06F 2212/452: Instruction code
- G06F 2212/6024: History based prefetching
- G06F 2212/657: Virtual address space management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

## Claims

### Claim 1

A device comprising:
a controller configurable to receive an access request from a peripheral, wherein the access request includes a memory address; and
a cache configuration register coupled to the controller and configured to store a first mask bit associated with the peripheral,
wherein the controller is configurable to:
perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and
allocate, using the first output bit, a cache way to a cache tag associated with the memory address from the access request.

### Claim 2 (depends on 1)

The device of claim 1, wherein the controller is configurable to allocate the cache way to the cache tag using the first output bit and a second pointer bit.

### Claim 3 (depends on 2)

The device of claim 2,
wherein the first pointer bit is a least significant bit of a pointer, and
wherein the second pointer bit is a most significant bit of the pointer.

### Claim 4 (depends on 1)

The device of claim 1, wherein the controller is configurable to:
retrieve a second mask bit from the cache configuration register;
perform the first logical operation with a second pointer bit and the second mask bit to generate a second output bit; and
allocate the cache way to the cache tag using the first output bit and the second output bit.

### Claim 5 (depends on 4)

The device of claim 4,
wherein the first pointer bit is a first least significant bit of a pointer,
wherein the second pointer bit is a second least significant bit of the pointer,
wherein the pointer further includes a most significant pointer bit, and
wherein the controller is configurable to allocate the cache way to the cache tag using the first output bit, the second output bit, and the most significant pointer bit.

### Claim 6 (depends on 5)

The device of claim 5,
wherein the most significant pointer bit is a first most significant pointer bit,
wherein the pointer further includes a second most significant pointer bit, and
wherein the controller is configurable to allocate the cache way to the cache tag using the first output bit, the second output bit, the first most significant pointer bit, and the second most significant pointer bit.

### Claim 7 (depends on 1)

The device of claim 1,
wherein the cache configuration register is configured to store the first mask bit associated with a membership of the peripheral, and
wherein the membership of the peripheral indicates whether the peripheral is associated with a real-time priority or a non-real-time priority.

### Claim 8 (depends on 1)

The device of claim 1,
wherein the cache configuration register is configured to store a second mask bit associated with the peripheral, and
wherein the controller is configurable to:
perform a second logical operation with the first output bit and the second mask bit to generate a first identifier bit; and
allocate the cache way to the cache tag using the first identifier bit.

### Claim 9 (depends on 8)

The device of claim 8,
wherein the cache configuration register is configured to:
store a third mask bit associated with the peripheral; and
store a fourth mask bit associated with the peripheral, and
wherein the controller is configurable to:
perform the first logical operation with a second pointer bit and the third mask bit to generate a second output bit;
perform the second logical operation with the second output bit and the fourth mask bit to generate a second identifier bit; and
allocate the cache way to the cache tag using the first identifier bit and the second identifier bit.

### Claim 10 (depends on 1)

The device of claim 1,
wherein the first mask bit is a bit in an AND mask, and
wherein the first logical operation is an AND operation.

### Claim 11 (depends on 1)

The device of claim 1,
wherein the first mask bit is a bit in an OR mask, and
wherein the first logical operation is an OR operation.

### Claim 12 (depends on 1)

The device of claim 1, wherein the first pointer bit is a bit in a randomly generated pointer.

### Claim 13

A method comprising:
receiving an access request from a peripheral, wherein the access request includes a memory address;
retrieving a first mask bit associated with the peripheral from a cache configuration register;
performing a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and
allocating, using the first output bit, a cache way to a cache tag associated with the memory address from the access request.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
retrieving a second mask bit associated with the peripheral from the cache configuration register;
performing the first logical operation with a second pointer bit and the second mask bit to generate a second output bit; and
allocating the cache way to the cache tag using the first output bit and the second output bit.

### Claim 15 (depends on 14)

The method of claim 14,
wherein the first pointer bit is a first least significant bit of a pointer,
wherein the second pointer bit is a second least significant bit of the pointer,
wherein the pointer further includes a most significant pointer bit, and
wherein the method further comprises allocating the cache way to the cache tag using the first output bit, the second output bit, and the most significant pointer bit.

### Claim 16 (depends on 15)

The method of claim 15,
wherein the most significant pointer bit is a first most significant pointer bit,
wherein the pointer further includes a second most significant pointer bit, and
wherein the method further comprises allocating the cache way to the cache tag using the first output bit, the second output bit, the first most significant pointer bit, and the second most significant pointer bit.

### Claim 17 (depends on 13)

The method of claim 13, further comprising:
retrieving a second mask bit associated with the peripheral from the cache configuration register;
performing a second logical operation with the first output bit and the second mask bit to generate a first identifier bit; and
allocating the cache way to the cache tag using the first identifier bit.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
retrieving a third mask bit associated with the peripheral from the cache configuration register;
retrieving a fourth mask bit associated with the peripheral from the cache configuration register;
performing the first logical operation with a second pointer bit and the third mask bit to generate a second output bit;
performing the second logical operation with the second output bit and the fourth mask bit to generate a second identifier bit; and
allocating the cache way to the cache tag using the first identifier bit and the second identifier bit.

### Claim 19

A system comprising:
a memory cache including a cache way;
a peripheral;
a cache controller configurable to receive an access request from the peripheral, wherein the access request includes a memory address; and
a cache configuration register coupled to the cache controller and configured to store a first mask bit associated with the peripheral,
wherein the cache controller is configurable to:
perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and
allocate, using the first output bit, the cache way to a cache tag associated with the memory address using the first output bit from the access request.

### Claim 20 (depends on 19)

The system of claim 19,
wherein the cache configuration register is configured to store a second mask bit associated with the peripheral, and
wherein the cache controller is configurable to:
perform a second logical operation with the first output bit and the second mask bit to generate a first identifier bit; and
allocate the cache way to the cache tag using the first identifier bit.