# US 12,761,999 B2 · Out-of-band error reporting in a data center > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,761,999 B2 - Document ID: US12761999B2 - Status: Granted - Kind: B2 - Application number: 18/999,504 - Filed: 2024-12-23 - Published: 2026-04-16 - Granted: 2026-10-13 - Earliest claimed: 2024-10-15 - Assignees: Advanced Micro Devices, Inc.; ATI Technologies ULC - Applicants: Advanced Micro Devices, Inc.; Ati Technologies Ulc - Inventors: Vilas Sridharan; Kabita Rani Saha; Carlos Vallin; Maher Mounir Moghabghab; Vignesh Vaidhyanathan Seshan; Fabio Giorgio Gulino; Alexander Kaganov - Web page: https://patentgrep.com/patent/US12761999B2 ## CPC - G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers} - G06F 11/0766: {Error or fault reporting or storing} - G06F 11/0784: {Routing of error reports, e.g. with a specific transmission path or data flow} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus includes a storage location that is accessible to control plane circuitry and first circuitry configured to receive an interrupt indicating a fatal error. The first circuitry is also configured to provide, in response to the interrupt, first information indicating the fatal error to a data plane entity and second information indicating the fatal error to the storage location. The second information in the storage location is accessible via a control plane connection independently of the data plane entity initiating one or more recovery actions in response to receiving the first information. A system management controller (SMC) or a baseboard management controller (BMC) can be configured to access the second information in the storage location and convey the second information to control plane circuitry in a data center. ## Claims ### Claim 1 An apparatus comprising: a storage location that is accessible to control plane circuitry; and first circuitry configured to receive an interrupt indicating a fatal error and provide, in response to the interrupt, first information indicating the fatal error to a data plane entity and second information indicating the fatal error to the storage location, wherein the second information in the storage location is accessible via a control plane connection independently of the data plane entity initiating at least one recovery action in response to receiving the first information. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising: at least one of a system management controller (SMC) or a baseboard management controller (BMC) configured to access the second information in the storage location and convey the second information to control plane circuitry in a data center. ### Claim 3 (depends on 1) The apparatus of claim 1, further comprising: second circuitry configured to implement the data plane entity; and third circuitry configured to implement an accelerator circuit, wherein the data plane entity is configured to support the accelerator circuit, and wherein the third circuitry comprises the first circuitry. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the data plane entity comprises a driver that is configured to initiate the at least one recovery action in data plane circuitry of the accelerator circuit. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the driver is configured to initiate a device reset of the accelerator circuit in response to receiving the first information indicating the fatal error. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the first circuitry is configured to provide the second information to a location that survives the device reset of the accelerator circuit. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the first circuitry is configured to convey the second information to an external entity via the control plane connection concurrently with the driver performing the device reset of the accelerator circuit. ### Claim 8 (depends on 6) The apparatus of claim 6, wherein the first circuitry is configured to convey the second information to an external entity via the control plane connection subsequent to the driver performing the device reset of the accelerator circuit. ### Claim 9 A method comprising: receiving an interrupt indicating a fatal error; providing, in response to the interrupt, first information indicating the fatal error to a driver and second information indicating the fatal error to a location accessible to first circuitry that provides a control plane connection to an external entity; and conveying the second information from the first circuitry to the external entity via the control plane connection independently of the driver initiating at least one recovery action in response to receiving the first information. ### Claim 10 (depends on 9) The method of claim 9, further comprising: initiating, at the driver, the at least one recovery action in data plane circuitry of an accelerator circuit. ### Claim 11 (depends on 10) The method of claim 10, wherein initiating the at least one recovery action comprises initiating a device reset of the accelerator circuit in response to the driver receiving the first information indicating the fatal error. ### Claim 12 (depends on 11) The method of claim 11, wherein providing the second information to the location comprises providing the second information to a location that survives the device reset of the accelerator circuit. ### Claim 13 (depends on 12) The method of claim 12, wherein conveying the second information from the first circuitry to the external entity comprises conveying the second information to the external entity via the control plane connection concurrently with performing the device reset of the accelerator circuit. ### Claim 14 (depends on 13) The method of claim 13, wherein conveying the second information from the first circuitry to the external entity comprises conveying the second information to the external entity via the control plane connection subsequent to performing the device reset of the accelerator circuit. ### Claim 15 An accelerator circuit comprising: first circuitry configured to implement a first controller; and second circuitry configured to implement a second controller that provides a control plane connection between the accelerator circuit and an external entity, wherein the first controller provides, in response to a fatal error in data plane circuitry of the accelerator circuit, first information indicating the fatal error to a driver and second information indicating the fatal error to a location accessible to the second controller, wherein the second controller conveys the second information to the external entity via the control plane connection independently of the driver initiating at least one recovery action in response to receiving the first information. ### Claim 16 (depends on 15) The accelerator circuit of claim 15, wherein the driver is configured to initiate a device reset of the accelerator circuit in response to receiving the first information indicating the fatal error. ### Claim 17 (depends on 16) The accelerator circuit of claim 16, wherein the first controller is configured to provide the second information to a location that survives the device reset of the accelerator circuit. ### Claim 18 (depends on 17) The accelerator circuit of claim 17, wherein the second controller conveys the second information to the external entity via the control plane connection concurrently with the driver performing the device reset of the accelerator circuit. ### Claim 19 (depends on 17) The accelerator circuit of claim 17, wherein the second controller conveys the second information to an external entity via the control plane connection subsequent to the driver performing the device reset of the accelerator circuit. ### Claim 20 (depends on 15) The accelerator circuit of claim 15, further comprising: third circuitry configured to implement at least one of a graphics processing unit (GPU) a hardware accelerator for machine learning, a hardware accelerator for deep learning, or a hardware accelerator for high-performance computing.