# US 12,761,998 B2 · Streaming engine with deferred exception reporting

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- Number: US 12,761,998 B2
- Document ID: US12761998B2
- Status: Granted
- Kind: B2
- Application number: 18/892,677
- Filed: 2024-09-23
- Published: 2025-01-09
- Granted: 2026-10-13
- Earliest claimed: 2013-07-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Joseph Zbiciak; Timothy D. Anderson; Duc Bui; Kai Chirca
- Web page: https://patentgrep.com/patent/US12761998B2

## CPC

- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 9/30014: {with variable precision}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/30112: {comprising data of variable length}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F 9/3867: {using instruction pipelines}
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 11/0721: {within a central processing unit [CPU]}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/27: Built-in tests
- G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)}
- G06F 11/3648: {using additional hardware}
- G06F 12/0862: with prefetch
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 13/1673: {using buffers}
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F 2212/452: Instruction code
- G06F 2212/602: Details relating to cache prefetching
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

## Claims

### Claim 1

A circuit device comprising:
a processor core configured to execute an instruction that specifies a data stream that includes a first data element; and
a cache memory configured to store a portion of the data stream;
a cache controller coupled to the processor core and to the cache memory, wherein the cache controller includes:
an interface coupled to the cache memory and configured to request the first data element; and
a set of fault registers, wherein the cache controller is configured to:
detect a fault associated with the first data element;
based on the fault, store an identifier of the fault in the set of fault registers;
receive a request from the processor core for the first data element;
defer reporting of the fault to the processor core until the request is received; and
in a debug mode, provide the identifier of the fault from the set of fault registers to a debugger.

### Claim 2 (depends on 1)

The circuit device of claim 1, wherein:
the cache controller includes an address generator coupled to the interface and configured to produce a set of addresses associated with the data stream;
the set of addresses includes a first address associated with the first data element; and
the cache controller is configured to:
based on the fault, store the first address in the set of fault registers; and
in the debug mode, provide the first address from the set of fault registers to the debugger.

### Claim 3 (depends on 2)

The circuit device of claim 2, wherein the identifier specifies whether an address rollover occurred during the producing of the set of addresses.

### Claim 4 (depends on 1)

The circuit device of claim 1, wherein the identifier specifies whether an error checking code error occurred.

### Claim 5 (depends on 1)

The circuit device of claim 1, wherein:
the cache controller includes a storage circuit coupled to the interface; and
the storage circuit is configured to store the first data element and a flag that indicates whether the fault occurred with respect to the first data element.

### Claim 6 (depends on 5)

The circuit device of claim 5, wherein the cache controller is configured to provide, to the processor core, the first data element and the flag.

### Claim 7 (depends on 6)

The circuit device of claim 6, wherein the processor core is configured to take an exception based on the flag.

### Claim 8 (depends on 5)

The circuit device of claim 5, wherein the identifier specifies whether the fault is associated with the storage circuit.

### Claim 9 (depends on 1)

The circuit device of claim 1, wherein the identifier specifies whether the fault is associated with the cache memory.

### Claim 10 (depends on 1)

The circuit device of claim 1, wherein the cache memory is a level-two (L2) cache memory.

### Claim 11 (depends on 10)

The circuit device of claim 10, wherein:
the circuit device further comprises a level-one (L1) cache memory; and
the cache controller is coupled between the L2 cache memory and the processor core in parallel with the L1 cache memory.

### Claim 12

A device comprising:
a cache memory controller that includes:
an interface configured to couple to a cache memory;
a head register coupled to the interface and configured to couple to a processor core; and
a set of fault registers;
wherein the cache memory controller is configured to, based on an instruction that specifies a data stream:
provide, via the interface, a set of memory accesses to retrieve at least a portion of the data stream from the cache memory;
receive, via the interface, the at least a portion of the data stream from the cache memory;
determine whether a fault occurred associated with a first data element of the data stream;
based on the fault, store an identifier of the fault in the set of fault registers;
receive a request from the processor core to provide the first data element from the head register;
defer reporting of the fault to the processor core until the request is received; and
in a debug mode, provide the identifier of the fault from the set of fault registers.

### Claim 13 (depends on 12)

The device of claim 12, wherein:
the cache memory controller includes an address generator coupled to the interface and configured to produce a set of addresses associated with the data stream;
the set of addresses includes a first address associated with the first data element; and
the cache memory controller is configured to:
based on the fault, store the first address in the set of fault registers; and
in the debug mode, provide the first address from the set of fault registers.

### Claim 14 (depends on 13)

The device of claim 13, wherein the identifier specifies whether the fault is associated with the producing of the set of addresses.

### Claim 15 (depends on 12)

The device of claim 12, wherein the identifier specifies whether an error checking code error occurred.

### Claim 16 (depends on 12)

The device of claim 12, wherein the reporting of the fault includes providing, to the processor core, the first data element and a flag that identifies whether the fault occurred with respect to the first data element.

### Claim 17

A method comprising:
receiving a stream open instruction that specifies a set of data; and
based on the stream open instruction, performing by a cache controller:
requesting a first data element of the set of data;
detecting a fault associated with the first data element;
storing an identifier of the fault in a set of fault registers;
delaying reporting of the fault to a processor core until a request is received from the processor core for the first data element;
entering into a debug mode; and
in the debug mode, providing the identifier of the fault.

### Claim 18 (depends on 17)

The method of claim 17 further comprising, performing by the cache controller:
generating a first address associated with the first data element;
based on the fault, storing the first address in the set of fault registers; and
in the debug mode, providing the first address.

### Claim 19 (depends on 17)

The method of claim 17 further comprising, performing by the cache controller:
storing the first data element and a flag that indicates whether the fault occurred with respect to the first data element in a storage circuit between the detecting of the fault and the reporting of the fault.

### Claim 20 (depends on 19)

The method of claim 19, wherein the reporting of the fault includes providing the first data element and the flag.