Replicating logic blocks to enable increased throughput with sequential enabling of input register blocks

A method of operating a datapath pipeline, the method comprising:

• enabling each of a set of input register blocks in turn on successive clock cycles to pass data into a plurality of parallel logic paths;
• processing the data in each of the parallel logic paths over a plurality of clock cycles, wherein the datapath pipeline comprises an intermediate multiplexer connected to a subset of the parallel logic paths, and wherein the datapath pipeline comprises a block of logic between a first multiplexer and the intermediate multiplexer;
• combining, using the intermediate multiplexer, the subset of the parallel logic paths into a single output;
• using the first multiplexer to select an output from each of the parallel logic paths in turn on successive clock cycles;
• and
• enabling a single output register circuit connected to an output of the first multiplexer on all clock cycles to receive data transmitted by the first multiplexer from the parallel logic paths in turn on successive clock cycles.

A non-transitory computer-readable storage medium comprising a computer program that is configured to be executed by one or more processors, the computer program including instructions that are configured to operate a datapath pipeline to:

• enable each of a set of input register blocks in turn on successive clock cycles to pass data into a plurality of parallel logic paths;
• process the data in each of the parallel logic paths over a plurality of clock cycles, wherein the datapath pipeline comprises an intermediate multiplexer connected to a subset of the parallel logic paths, and wherein the datapath pipeline comprises a block of logic between a first multiplexer and the intermediate multiplexer;
• combine, using the intermediate multiplexer, the subset of the parallel logic paths into a single output;
• use the first multiplexer to select an output from each logic path in turn on successive clock cycles;
• and
• enable a single output register circuit connected to an output of the first multiplexer on all clock cycles to receive data transmitted by the first multiplexer from the parallel logic paths in turn on successive clock cycles.