Arithmetic combination operation

A method of operating an apparatus comprising instruction decoder circuitry configured to decode program instructions, and processing circuitry configured to perform data processing in response to the instructions decoded by the instruction decoder, the method comprising:

• with the instruction decoder circuitry in response to a mixed-element-combination instruction specifying one or more first architectural registers and one or more second architectural registers, to trigger the processing circuitry to perform a mixed-element-combination operation, the mixed-element-combination instruction encoding element information identifying a set of elements in the one or more second architectural registers;
• with the processing circuitry:
• performing at least one arithmetic operation to combine each first element of a set of first elements from contiguous positions in the one or more first architectural registers with a corresponding second element of a set of second elements selected from the one or more second architectural registers according to the element information to generate a set of intermediate result elements;
• and
• combining the set of intermediate result elements to generate a result element,
• wherein a first element size of each first element of the set of first elements is different to a second element size of each second element of the set of second elements.

A computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising:

• instruction decoder program logic configured to decode program instructions;
• processing program logic configured to perform data processing in response to the instructions decoded by the instruction decoder program logic;
• wherein:
• the instruction decoder program logic is responsive to a mixed-element-combination instruction specifying one or more first storage structures simulating one or more first architectural registers and one or more second storage structures simulating one or more second architectural registers, to trigger the processing program logic to perform a mixed-element-combination operation, the mixed-element-combination instruction encoding element information identifying a set of elements in the one or more second storage structures;
• the processing program logic is configured, when performing the mixed-element-combination operation:
• to perform at least one arithmetic operation to combine each first element of a set of first elements from contiguous positions in the one or more first storage structures with a corresponding second element of a set of second elements selected from the one or more second storage structures according to the element information to generate a set of intermediate result elements;
• and
• to combine the set of intermediate result elements to generate a result element;
• and
• a first element size of each first element of the set of first elements is different to a second element size of each second element of the set of second elements.