# US 12,761,918 B2 · System and method for handling floating point hardware exception > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,761,918 B2 - Document ID: US12761918B2 - Status: Granted - Kind: B2 - Application number: 17/686,682 - Filed: 2022-03-04 - Published: 2022-06-16 - Granted: 2026-10-13 - Earliest claimed: 2019-12-19 - Assignees: Marvell Asia Pte Ltd - Applicants: Marvell Asia Pte Ltd - Inventors: Chia-Hsin Chen; Avinash Sodani; Ulf Hanebutte; Rishan Tan; Soumya Gollamudi - Web page: https://patentgrep.com/patent/US12761918B2 ## CPC - G06F 9/3001: {Arithmetic instructions} - G06F 7/49905: {Exception handling} - G06F 9/30181: {Instruction operation extension or modification} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F 9/3865: {using deferred exception handling, e.g. exception flags} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method includes receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data. The method includes determining whether the received input data is a qnan (quiet not-a-number) or whether the received input data is an snan (signaling not-a-number) prior to performing the floating point arithmetic operation. The method also includes converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is either qnan or snan, wherein the converting eliminates special handling associated with the floating point arithmetic operation on the input data being either qnan or snan. ## Claims ### Claim 1 A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on each received input data using a single processing path; determining whether the input data is a quiet not-a-number (qnan) or whether the input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; and converting a value of the input data to a modified value prior to performing the floating point arithmetic operation if the input data is either the qnan or the snan, wherein the converting eliminates special handling by causing the floating point arithmetic operation to be performed on the input data using the single processing path to generate an output result. ### Claim 2 (depends on 1) The method of claim 1, wherein the floating point arithmetic operation is selected from one of a negate operation, converting a first floating point to a second floating point operation if the input data is greater than a number and converting from a third floating point to a fourth floating point operation if the input data is less than the number, or converting from floating point to integer value operation. ### Claim 3 (depends on 1) The method of claim 1 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception. ### Claim 4 (depends on 3) The method of claim 3 further comprising setting a value of the output result to zero if the value of the output result is a denormal number. ### Claim 5 (depends on 3) The method of claim 3 further comprising setting a value of the output result to a maximum supported number if the value of the output result is a positive infinity, and setting the value of the output result to a minimum supported number if the value of the output result is a negative infinity. ### Claim 6 (depends on 1) The method of claim 1, wherein the converting of the value of the input data to the modified value is setting a value of the input data to zero if the input data is the qnan. ### Claim 7 (depends on 6) The method of claim 6 further comprising generating an un-initialized flag associated with the input data. ### Claim 8 (depends on 1) The method of claim 1, wherein the converting of the value of the input data to the modified value is setting a value of the input data to zero if the input data is the snan. ### Claim 9 (depends on 8) The method of claim 8 further comprising generating an un-initialized flag associated with the converting. ### Claim 10 A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on each received input data using a single processing path; determining whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; and setting the input data to value zero if the input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation on the input data by the floating point operating unit, and wherein the setting causes the floating point arithmetic operation to be performed on the input data using the single processing path to generate an output result. ### Claim 11 (depends on 10) The method of claim 10, wherein the floating point arithmetic operation is selected from one of a negate operation, converting a first floating point to a second floating point operation if the input data is greater than a number and converting from a third floating point to a fourth floating point operation if the input data is less than the number, or converting from floating point to integer value operation. ### Claim 12 (depends on 10) The method of claim 10 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception. ### Claim 13 (depends on 12) The method of claim 12 further comprising setting a value of the output result to zero if the value of the output result is a denormal number. ### Claim 14 (depends on 12) The method of claim 12 further comprising setting a value of the output result to a maximum supported number if the value of the output result is a positive infinity, and setting the value of the output result to a minimum supported number if the value of the output result is a negative infinity. ### Claim 15 (depends on 10) The method of claim 10 further comprising generating an un-initialized flag associated with the input data in response to the setting. ### Claim 16 A system comprising: a logic engine configured to receive an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on each received input data using a single processing path, determine whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; and a convertor engine configured to convert a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is either the qnan or the snan, wherein the converting eliminates special handling by causing the floating point arithmetic operation to be performed on the input data using the single processing path to generate an output result. ### Claim 17 (depends on 16) The system of claim 16, wherein the floating point arithmetic operation is selected from one of a negate operation, converting a first floating point to a second floating point operation if the input data is greater than a number and converting from a third floating point to a fourth floating point operation if the input data is less than the number, or converting from floating point to integer value operation. ### Claim 18 (depends on 16) The system of claim 16, wherein the logic engine is configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception. ### Claim 19 (depends on 18) The system of claim 18, wherein the logic engine is configured to set a value of the output result to zero if a value of the output result is a denormal number. ### Claim 20 (depends on 18) The system of claim 18, wherein the logic engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity. ### Claim 21 (depends on 16) The system of claim 16, wherein the convertor engine is configured to set a value of the input data to zero if the input data is the qnan. ### Claim 22 (depends on 21) The system of claim 21, wherein the logic engine is configured to generate an un-initialized flag associated with the input data being qnan. ### Claim 23 (depends on 16) The system of claim 16, wherein the convertor engine is configured to set a value of the input data to zero if the input data is the snan. ### Claim 24 (depends on 23) The system of claim 23, wherein the logic engine is configured to generate an un-initialized flag associated with the input data being snan. ### Claim 25 A system comprising: a means for receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on each received input data using a single processing path; a means for determining whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; and a means for setting the input data to value zero if the input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation on the input data by the floating point operating unit, and wherein the setting causes the floating point arithmetic operation to be performed on the input data using the single processing path to generate an output result. ### Claim 26 (depends on 25) The system of claim 25 further comprising a means for determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception. ### Claim 27 (depends on 26) The system of claim 26 further comprising a means for setting a value of the output result to zero if the value of the output result is a denormal number. ### Claim 28 (depends on 26) The system of claim 26 further comprising a means for setting a value of the output result to a maximum supported number if the value of the output result is a positive infinity, and setting the value of the output result to a minimum supported number if the value of the output result is a negative infinity. ### Claim 29 (depends on 25) The system of claim 25 further comprising a means for generating an un-initialized flag associated with the input data in response to determining that the received input data is a qnan or a snan.