# US 12,761,876 B2 · Flexible architecture for floating-point and integer compute-in-memory

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- Number: US 12,761,876 B2
- Document ID: US12761876B2
- Status: Granted
- Kind: B2
- Application number: 19/542,519
- Filed: 2026-02-17
- Published: 2026-08-20
- Granted: 2026-10-13
- Earliest claimed: 2025-02-18
- Assignees: OpenAI OpCo, LLC
- Applicants: OpenAI Opco, LLC
- Inventors: Mohammed Elneanaei Abdelmoneem Fouda
- Web page: https://patentgrep.com/patent/US12761876B2

## CPC

- G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)}
- G06F 7/4876: {Multiplying}
- G06F 2207/3824: Accepting both fixed-point and floating-point numbers
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The disclosure describes systems and methods for mixed-mode, mixed-precision computation using a configurable compute engine for vector-matrix operations. A processing system selects a floating-point mode or an integer mode, selects a precision, and gates inactive datapath portions to reduce energy and stabilize latency. Streaming and stationary operand registers supply compute circuitry that, in floating-point mode, forms a mantissa product and product exponent, combines signs, and aligns the product using a power-of-two generator that drives a selection network based on the exponent. In integer mode, the same selection network performs integer multiplication from bitwise inputs, with sign handling applying two's-complement correction prior to accumulation. Parallel adder trees feed a hierarchical output accumulator sized to the selected precision, and normalization performs leading-one detection, mode-dependent exponent correction, rounding, and zero flushing. Optional dequantization folds scale tensors into the exponent path, and implementations support compute-in-memory or conventional accelerators.

## Claims

### Claim 1

A computing system, comprising:
a processing system including one or more processors; and
a compute engine coupled to the processing system, wherein
the processing system is configured to:
select a mode from a floating-point mode or an integer mode;
select a precision from multiple precisions; and
gate portions of the compute engine responsive to the selected mode and the selected precision; and
the compute engine comprises:
operand registers for operand values;
compute circuitry configured, in the floating-point mode, to produce a mantissa product and a product exponent and to combine signs;
alignment circuitry comprising a power-of-two generator and a selection network coupled to the compute circuitry, the alignment circuitry being configured to:
in the floating-point mode, align the mantissa product as part of multiplication using a power-of-two value corresponding to the product exponent; and
in the integer mode, drive the selection network to perform integer multiplications of the operand values;
sign-handling circuitry configured to manage negative values, including two's-complement handling in the integer mode prior to accumulation;
accumulation circuitry comprising a plurality of parallel adder trees and a hierarchical output accumulator; and
normalization circuitry configured to form an output value in a numeric format.

### Claim 2 (depends on 1)

The system of claim 1, wherein the operand registers comprise streaming operand registers and stationary operand registers.

### Claim 3 (depends on 1)

The system of claim 1, wherein exponent alignment during the multiplication is performed by the alignment circuitry, the alignment circuitry comprising the power-of-two generator driving the selection network to align the mantissa product based on the product exponent.

### Claim 4 (depends on 1)

The system of claim 1, wherein the power-of-two generator is an address decoder, a lookup table, or a combinational logic configured to produce mutually exclusive control lines corresponding to the power-of-two value.

### Claim 5 (depends on 1)

The system of claim 1, wherein the power-of-two value is 2 raised to the product exponent (2{circumflex over ( )}E).

### Claim 6 (depends on 1)

The system of claim 1, wherein responsive to the selected mode or the precision, portions of the plurality of parallel adder trees and the hierarchical output accumulator are disabled.

### Claim 7 (depends on 1)

The system of claim 1, wherein the normalization circuitry is configured to perform one or more of: leading-one detection, compute an output exponent with a mode-dependent correction, apply rounding selected from truncate, round-to-nearest, round-to-even, or flush to zero responsive to a zero flag.

### Claim 8 (depends on 7)

The system of claim 7, further comprising:
dequantization circuitry configured to fuse scale tensors and streaming operands into the output exponent, the dequantization circuitry being within the normalization circuitry.

### Claim 9 (depends on 1)

The system of claim 1, wherein the compute circuitry includes mantissa product logic configured to preserve subnormal values by enforcing a zero immediately after the radix point via a bitwise OR mechanism.

### Claim 10 (depends on 1)

The computing system of claim 1, wherein
the operand registers comprise stationary operand registers configured to store a matrix operand and streaming operand registers configured to store a vector operand, and
the compute circuitry performs a vector-matrix multiplication by multiplying elements of the vector operand by corresponding elements of the matrix operand and accumulating products to form dot-product results.

### Claim 11 (depends on 1)

The computing system of claim 1, wherein:
selecting the precision comprises selecting among at least a first floating-point precision, a second floating-point precision different from the first floating-point precision, and at least one integer precision, and
gating the portions of the compute engine comprises selectively enabling a subset of the plurality of parallel adder trees based on the selected precision.

### Claim 12 (depends on 1)

The computing system of claim 1, wherein
the compute engine further comprises multiplication multiplexers arranged to selectively route integer operand bits or integer partial products to the accumulation circuitry, and
in the integer mode, driving the selection network comprises controlling the multiplication multiplexers to implement an integer multiplication operation.

### Claim 13 (depends on 1)

The computing system of claim 1, wherein: in the floating-point mode, the compute circuitry and the accumulation circuitry operate as a fused multiply-and-add datapath in which the mantissa product is aligned based on the product exponent.

### Claim 14 (depends on 1)

The computing system of claim 1, further comprising:
pre-output accumulator circuitry coupled between the plurality of parallel adder trees and the hierarchical output accumulator, the pre-output accumulator circuitry being configured to condition partial sums prior to entry into the hierarchical output accumulator by applying sign correction.

### Claim 15 (depends on 1)

The computing system of claim 1, wherein the hierarchical output accumulator comprises a plurality of accumulator stages arranged to:
accumulate partial sums across multiple evaluation phases, and
combine accumulated results from the plurality of accumulator stages to produce the output value.

### Claim 16

A method, comprising:
selecting, by a processing system, a mode from a floating-point mode or an integer mode;
selecting, by the processing system, a precision from multiple precisions;
gating, by the processing system, portions of a compute engine responsive to the selected mode and the selected precision;
producing, in the floating-point mode and by compute circuitry of the compute engine, a mantissa product and a product exponent and combining signs;
aligning, in the floating-point mode and by alignment circuitry comprising a power-of-two generator and a selection network coupled to the compute circuitry, the mantissa product as part of multiplication using a power-of-two value corresponding to the product exponent;
driving, in the integer mode and by the alignment circuitry, the selection network to perform integer multiplications of operand values;
managing negative values using sign-handling circuitry, including performing two's-complement handling in the integer mode prior to accumulation;
accumulating aligned products using accumulation circuitry comprising a plurality of parallel adder trees and a hierarchical output accumulator; and
normalizing an output sum using normalization circuitry to form an output value in a numeric format.

### Claim 17 (depends on 16)

The method of claim 16, wherein operand registers stage the operand values and include streaming operand registers and stationary operand registers.

### Claim 18 (depends on 16)

The method of claim 16, wherein exponent alignment during the multiplication is performed by the alignment circuitry, the alignment circuitry comprising the power-of-two generator driving the selection network to align the mantissa product based on the product exponent.

### Claim 19 (depends on 16)

The method of claim 16, wherein the power-of-two generator is an address decoder, a lookup table, and combinational logic configured to produce mutually exclusive control lines corresponding to the power-of-two value.

### Claim 20

An apparatus, comprising:
operand registers for operand values;
compute circuitry configured to produce a mantissa product and a product exponent;
alignment circuitry comprising a power-of-two generator and a selection network coupled to the compute circuitry, the alignment circuitry being configured to:
in a floating-point mode, align the mantissa product as part of multiplication using a power-of-two value corresponding to the product exponent; and
in an integer mode, drive the selection network to perform integer multiplications of the operand values;
sign-handling circuitry configured to manage negative values, including two's-complement handling in the integer mode prior to accumulation;
accumulation circuitry comprising a plurality of parallel adder trees and a hierarchical output accumulator; and
normalization circuitry configured to form an output value in a numeric format.