Chiplet-based storage device and method of transmitting control codes to chiplet

A memory controller comprising:

• a first chip configured to perform a first operation of the memory controller;
• a plurality of second chips configured to perform a second operation of the memory controller;
• a plurality of data links configured to connect the first chip and each of the plurality of second chips on a one-to-one basis and provide data transmission between the first chip and each of the plurality of second chips;
• a control link connected to the first chip and the plurality of second chips and configured to transmit a control code for performing the second operation of the plurality of second chips;
• a memory connected to the first chip and configured to store the control code,
• wherein the first chip is configured to:
• obtain the control code from the memory;
• and
• transmit the control code to the plurality of second chips at a same time through the control link, wherein transmitting of the control code is repeated until reception completion messages for the control code are received from all of the plurality of second chips,
• wherein, in response to power being applied to at least one of the plurality of second chips during a first transmission of the control code, the at least one of the plurality of second chips is configured to receive the control code starting from a middle part of the first transmission, and
• the at least one of the second chips is further configured to receive a front part of the control code during a second transmission subsequent to the first transmission to finish reception of an entire control code.