# US 12,761,801 B2 · Flash memory controller and flash memory access method

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- Number: US 12,761,801 B2
- Document ID: US12761801B2
- Status: Granted
- Kind: B2
- Application number: 18/901,733
- Filed: 2024-09-30
- Published: 2025-10-23
- Granted: 2026-10-13
- Earliest claimed: 2024-04-19
- Assignees: Silicon Motion, Inc.
- Applicants: Silicon Motion Inc.
- Inventors: Duen Yih Teng; Mao Ruei Li
- Web page: https://patentgrep.com/patent/US12761801B2

## CPC

- G06F 3/0613: {in relation to throughput}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A flash memory controller and a flash memory access method are provided. The flash memory controller comprises a decoder, performing a decoding operation based on a base matrix of a quasi-cyclic low-density parity-check code and the channel values read from a flash memory. The decoder comprises a variable node block, a V2C shift block, a check node block, which are serially coupled. The decoder further comprises a status data shift block, which is parallelly coupled with the check node block, circularly shifts the status data of the check node block and feeds back to the check node block. Due to the number of serially coupled blocks is only three, the convergence speed of the iterative decoding process is improved, thereby the flash memory access performance is enhanced.

## Claims

### Claim 1

A flash memory controller for accessing a flash memory, comprising:
a first memory for storing a program code;
a microprocessor for executing the program code to control access to the flash memory; and
a decoder for receiving channel values read from the flash memory and performing a decoding process of a quasi-cyclic low-density parity-check (QC-LDPC) code, wherein the decoding process of the decoder involves a plurality of Q messages and a plurality of R messages, and the decoder comprises:
a shift parameter unit for generating a first shift parameter and a second shift parameter based on a X×Y base matrix of the QC-LDPC code;
a second memory for storing the plurality of Q messages;
a third memory for storing the plurality of R messages;
a variable node block for updating the plurality of Q messages based on the channel values read from the flash memory and the plurality of R messages;
a first shift block for generating a plurality of Q′ messages based on the plurality of Q messages and the first shift parameter;
a second shift block for generating a plurality of status data S′; and
a check node block for updating the plurality of R messages and outputting a plurality of status data S based on the plurality of Q′ messages and the plurality of status data S′, wherein each status data S comprises a minimum value, a second minimum value, an index of the minimum value, and a global sign value;
wherein the second shift block receives the plurality of status data S and performs circular shift according to the second shift parameter to generate the plurality of status data S′.

### Claim 2 (depends on 1)

The flash memory controller according to claim 1, wherein the check node block comprises a sub-block, the second shift block comprises a shift unit, the second shift parameter comprises a sub-parameter, the plurality of status data S comprise a first status data S through a Kth status data S with K being an integer, the plurality of status data S′ comprises a first status data S′ through a Kth status data S′, and the plurality of Q′ messages comprise a first Q′ message through a Kth Q′ message, the plurality of R messages comprise a first R message through a Kth R message, and
the shift unit of the second shift block receives the first status data S through the Kth status data S, and performs circular shift according to the sub-parameter of the second shift parameter, and generates the first status data S′ through the Kth status data S′; and
the sub-block of the check node block comprises a first check node unit through a Kth check node unit, wherein the kth check node unit receives the kth Q′ message and the kth status data S′, updates the kth R message and outputs the kth status data S with k being an integer from 1 to K.

### Claim 3 (depends on 2)

The flash memory controller according to claim 2, wherein the check node block comprises X sub-blocks, each sub-block of the check node block comprises K check node units, the second shift block comprises X shift units, the second shift parameter comprises X sub-parameters, the plurality of status data S comprises X·K status data S, the plurality of status data S′ comprises X·K status data S′, the plurality of Q′ messages comprises (X·K) Q′ messages, and the plurality of R messages comprises (X·K) R messages.

### Claim 4 (depends on 1)

The flash memory controller according to claim 1, the shift parameter unit comprises:
a fourth memory for storing the X·Y base matrix; and
a pipeline register comprising a plurality of registers with each register being able of storing X values;
wherein each column of the base matrix is output sequentially to the pipeline register for each clock cycle, the first shift parameter output by the shift parameter unit is a difference between a first register and a second register in the pipeline register, and the second shift parameter output by the shift parameter unit is a difference between a third register and a fourth register in the pipeline register, wherein the first register is adjacent to the second register and the third register is adjacent to the fourth register.

### Claim 5 (depends on 4)

The flash memory controller according to claim 4, wherein the number of registers in the pipeline register is less than or equal to Y.

### Claim 6 (depends on 1)

The flash memory controller according to claim 1, wherein the first shift block and the second shift block are both Barrel shifters.

### Claim 7

A method for improving access efficiency of a flash memory, for use in a flash memory controller coupled to the flash memory, the method comprising:
receiving, by a decoder, channel values read from the flash memory; and
performing, by the decoder, a decoding process on the channel values in an iterative manner according to a parity check matrix of a quasi-cyclic low-density parity-check (QC-LDPC) code, wherein the decoding process involves a plurality of Q messages and a plurality of R messages, and the decoding process comprises the following steps:
calculating, using a shift parameter unit comprising a memory storing a base matrix and a pipeline register for storing a shift parameter matrix, a first shift parameter and a second shift parameter based on the shift parameter matrix, wherein the first shift parameter is a difference between a specific first column and a specific second column of the shift parameter matrix, the specific first column being adjacent to the specific second column, and the second shift parameter is a difference between a specific third column and a specific fourth column of the shift parameter matrix, the specific third column being adjacent to the specific fourth column;
updating, using a variable node block, the plurality of Q messages based on the channel values and the plurality of R messages;
performing circular shift, using a first shift block, on the plurality of Q messages to generate a plurality of Q′ messages according to the first shift parameter;
circularly shifting, using a second shift block, a plurality of status data S according to the second shift parameter to generate a plurality of status data S′, wherein each of the plurality of status data S comprises a minimum value, a second minimum value, an index of the minimum value, and a global sign value; and
updating, using a check node block, the plurality of R messages based on the plurality of Q′ messages and the plurality of status data S′ and outputting the plurality of status data S;
wherein the shift parameter unit outputs each column of the base matrix sequentially to the pipeline register for each clock cycle.

### Claim 8

A method for improving access efficiency of a flash memory, for use in a flash memory controller coupled to the flash memory, the method comprising:
receiving, by a decoder, channel values read from the flash memory; and
performing, by the decoder, a decoding process of a quasi-cyclic low-density parity-check (QC-LDPC) code, wherein the decoding process involves a plurality of Q messages and a plurality of R messages, and the decoding process comprises the following steps:
generating, using a shift parameter unit, a first shift parameter and a second shift parameter based on a X×Y base matrix of the QC-LDPC code;
updating, using a variable node block, the plurality of Q messages based on the channel values read from the flash memory and the plurality of R messages;
generating, using a first shift block, a plurality of Q′ messages based on the plurality of Q messages and the first shift parameter;
generating, using a second shift block, a plurality of status data S′ by performing circular shift on a plurality of status data S according to the second shift parameter; and
updating, using a check node block, the plurality of R messages and outputting the plurality of status data S based on the plurality of Q′ messages and the plurality of status data S′, wherein each status data S comprises a minimum value, a second minimum value, an index of the minimum value, and a global sign value.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the check node block comprises a sub-block, the second shift block comprises a shift unit, the second shift parameter comprises a sub-parameter, the plurality of status data S comprise a first status data S through a Kth status data S with K being an integer, the plurality of status data S′ comprises a first status data S′ through a Kth status data S′, and the plurality of Q′ messages comprise a first Q′ message through a Kth Q′ message, the plurality of R messages comprise a first R message through a Kth R message, and
the shift unit of the second shift block receives the first status data S through the Kth status data S, and performs circular shift according to the sub-parameter of the second shift parameter, and generates the first status data S′ through the Kth status data S′; and
the sub-block of the check node block comprises a first check node unit through a Kth check node unit, wherein the kth check node unit receives the kth Q′ message and the kth status data S′, updates the kth R message and outputs the kth status data S with k being an integer from 1 to K.

### Claim 10 (depends on 9)

The method according to claim 9, wherein the check node block comprises X sub-blocks, each sub-block of the check node block comprises K check node units, the second shift block comprises X shift units, the second shift parameter comprises X sub-parameters, the plurality of status data S comprises X·K status data S, the plurality of status data S′ comprises X·K status data S′, the plurality of Q′ messages comprises (X·K) Q′ messages, and the plurality of R messages comprises (X·K) R messages.

### Claim 11 (depends on 8)

The method according to claim 8, wherein the shift parameter unit comprises:
a fourth memory for storing the X·Y base matrix; and
a pipeline register comprising a plurality of registers with each register being capable of storing X values;
wherein each column of the base matrix is output sequentially to the pipeline register for each clock cycle, the first shift parameter output by the shift parameter unit is a difference between a first register and a second register in the pipeline register, and the second shift parameter output by the shift parameter unit is a difference between a third register and a fourth register in the pipeline register, wherein the first register is adjacent to the second register and the third register is adjacent to the fourth register.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the number of registers in the pipeline register is less than or equal to Y.

### Claim 13 (depends on 8)

The method according to claim 8, wherein the first shift block and the second shift block are both Barrel shifters.