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AssigneeQUALCOMM Incorporated
InventorsPrathviraj Shetty, Srikar Karnam Venkat Naga, Pranav Agrawal, Pankaj Kumar Sharma, Louis Louie, Amod Kumar, Shekar Babu Merla, Odelu Kukatla, Ravi Teja Mandavilli, Anshul Verma, Sampath Kumar Kulasekara, Sudhakar Chakali, Rajkumar Hariharan
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Various embodiments include methods for controlling memory utilization to accommodate changes in memory accessibility due to memory refreshes include controlling bandwidth of at least one processor based on a refresh rate of a memory. Some embodiments may include receiving the refresh rate of the memory at a memory controller, and determining whether the refresh rate of the memory violates a high or low memory refresh rate threshold, sending an instruction configured to reduce or restore the bandwidth of the at least one processor in response to the determination. In some embodiments the methods may be performed by a quality of service manager, which may be part of a memory controller.
A method implemented in a system on chip (SoC) for memory utilization control, comprising:
A system on chip (SoC), comprising:
A computing device, comprising:
A non-transitory, processor-readable medium having stored thereon processor-executable instructions configured to cause a processor to perform operations comprising:
Dependencies are inferred from the claim text.