Low-latency retimer with seamless clock switchover
AssigneeAstera Labs, Inc.
InventorsJitendra Mohan, Subbarao Arumilli, Charan Enugala, Chi Feng, Ken (Keqin) Han, Pulkit Khandelwal, Vikas Khandelwal, Casey Morrison, Enrique Musoll, Vivek Trivedi
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Abstract
A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.
Claims20
An integrated circuit component comprising:
- clock recovery circuitry to generate a first clock signal having a first frequency based on transitions in an incoming data signal;
- frequency-divider circuitry to generate, by frequency-dividing the first clock signal, a second clock signal having a second frequency N times lower than the first frequency, N being an integer greater than one;
- a clock generator to generate a third clock signal having a third frequency that nominally matches the second frequency;
- clock selection circuitry to:
- generate a fourth clock signal based on the second clock signal during a first time interval and based on the third clock signal during a second time interval;
- and
- frequency-multiply the fourth clock signal by N to generate a fifth clock signal having a frequency N times higher than the second frequency during the first time interval and a frequency N times higher than the third frequency during the second time interval;
- and
- core circuitry that is clocked by the fifth clock signal throughout the first and second time intervals.
A method of operation within an integrated circuit component, the method comprising:
- generating a first clock signal having a first frequency based on transitions in an incoming data signal;
- frequency-dividing the first clock signal to generate a second clock signal having a second frequency N times lower than the first frequency, N being an integer greater than one;
- generating a third clock signal having a third frequency that nominally matches the second frequency;
- generating a fourth clock signal based on the second clock signal during a first time interval and based on the third clock signal during a second time interval;
- frequency-multiplying the fourth clock signal by N to generate a fifth clock signal having a frequency N times higher than the second frequency during the first time interval and a frequency N times higher than the third frequency during the second time interval;
- and
- clocking core circuitry within the integrated circuit component with the fifth clock signal throughout the first and second time intervals.
An integrated circuit component comprising:
- means for generating a first clock signal having a first frequency based on transitions in an incoming data signal;
- means for frequency-dividing the first clock signal to generate a second clock signal having a second frequency N times lower than the first frequency, N being an integer greater than one;
- means for generating a third clock signal having a third frequency that nominally matches the second frequency;
- means for generating a fourth clock signal based on the second clock signal during a first time interval and based on the third clock signal during a second time interval;
- means for frequency-multiplying the fourth clock signal by N to generate a fifth clock signal having a frequency N times higher than the second frequency during the first time interval and a frequency N times higher than the third frequency during the second time interval;
- and
- means for clocking core circuitry within the integrated circuit component with the fifth clock signal throughout the first and second time intervals.
Dependencies are inferred from the claim text.